trashernet/trashernet/trashernet_mac.vhd

140 lines
4.1 KiB
VHDL
Raw Normal View History

2021-08-30 13:27:30 +02:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.trashernet_types.all;
entity trashernet_mac is
port(
-- Global
clk : in std_logic; -- Global clock
rst : in std_logic; -- Asynchronous reset
-- PHY signals
rx_data : in std_logic_vector(7 downto 0); -- RX Data
rx_data_valid : in std_logic; -- RX Data valid
rx_active : in std_logic; -- RX of packet in progress
tx_data : out std_logic_vector(7 downto 0); -- TX Data
tx_data_en : out std_logic; -- Transmitter enable
tx_data_ack : in std_logic; -- Latched data_tx
carrier_detect : in std_logic; -- Carrier detected
rx_error : in std_logic; -- Receive error
-- MAC signals
rx_mac_destination : out mac_addr_t; -- Destination MAC address
rx_mac_source : out mac_addr_t; -- Source MAC address
rx_mac_ethertype : out ethertype_t; -- Ethertype or length
rx_mac_data : out byte; -- Ethernet data (after Ethertype)
rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid
rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid
rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
rx_mac_crc_error : out std_logic -- End of packet, CRC invalid
);
end entity trashernet_mac;
architecture rtl of trashernet_mac is
signal crc : std_logic_vector(31 downto 0);
signal crc_ok : std_logic;
signal crc_clear : std_logic;
begin
rx : block
type state_t is (HEAD, PAYLOAD);
constant HEAD_LENGTH : integer := rx_mac_destination'length + rx_mac_source'length + rx_mac_ethertype'length;
constant CRC_LENGTH : integer := 4;
signal state : state_t;
signal sr_head : byte_vector(0 to HEAD_LENGTH - 1);
constant BYTE_COUNT_MAX : integer := maximum(HEAD_LENGTH, CRC_LENGTH) - 1;
signal byte_count : integer range 0 to BYTE_COUNT_MAX;
signal sr_payload : byte_vector(0 to 4);
constant ETH_POLYNOMIAL : std_logic_vector(crc'range) := x"04C11DB7";
begin
crc_inst : entity work.crc
generic map(
POLYNOMIAL => ETH_POLYNOMIAL,
START => x"FFFFFFFF",
FINAL_XOR => x"FFFFFFFF",
REVERSE_OUT => true
)
port map(
clk => clk,
rst => rst,
data => rx_data,
data_valid => rx_data_valid,
crc_clear => crc_clear,
crc_out => crc
);
crc_ok <= '1' when crc = x"2144DF1C" else '0';
main : process(clk, rst) is
begin
if rst then
byte_count <= 0;
rx_mac_valid <= '0';
rx_mac_crc_error <= '0';
rx_mac_crc_ok <= '0';
rx_mac_header_rcv <= '0';
crc_clear <= '0';
elsif rising_edge(clk) then
rx_mac_valid <= '0';
rx_mac_crc_error <= '0';
rx_mac_crc_ok <= '0';
rx_mac_header_rcv <= '0';
crc_clear <= '0';
case state is
when HEAD =>
if rx_data_valid then
sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & rx_data;
if byte_count = (HEAD_LENGTH - 1) then
state <= PAYLOAD;
byte_count <= 0;
rx_mac_header_rcv <= '1';
end if;
if (byte_count /= BYTE_COUNT_MAX) then
byte_count <= byte_count + 1;
end if;
end if;
when PAYLOAD =>
if rx_data_valid then
sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & rx_data;
if byte_count = CRC_LENGTH then
rx_mac_valid <= '1';
else
byte_count <= byte_count + 1;
end if;
end if;
if not rx_active then
rx_mac_crc_ok <= crc_ok;
rx_mac_crc_error <= not crc_ok;
end if;
if rx_error then
rx_mac_crc_error <= '1';
end if;
end case;
if (not rx_active) or rx_error then
byte_count <= 0;
state <= HEAD;
crc_clear <= '1';
end if;
end if;
end process main;
rx_mac_destination <= sr_head(0 to 5);
rx_mac_source <= sr_head(6 to 11);
rx_mac_ethertype <= sr_head(12 to 13);
rx_mac_data <= sr_payload(0);
end block rx;
end architecture rtl;