78 lines
2.2 KiB
VHDL
78 lines
2.2 KiB
VHDL
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- ledcon.vhd : Simple debug LED helper
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-- To blink or not blink.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity ledcon is
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generic(
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F_CLK : integer;
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BLINK : boolean_vector
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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sig : in std_logic_vector;
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led_n : out std_logic_vector
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);
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end entity ledcon;
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architecture RTL of ledcon is
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constant MS_CNT_MAX : integer := integer(round(real(F_CLK) * (1.0 * 10.0 ** (-3))));
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signal ms_cnt : integer range 0 to MS_CNT_MAX;
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signal ms_tick : std_logic;
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begin
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mstimer : process(clk, rst) is
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begin
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if rst then
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ms_cnt <= MS_CNT_MAX;
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elsif rising_edge(clk) then
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if (ms_cnt = 0) then
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ms_cnt <= MS_CNT_MAX;
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else
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ms_cnt <= ms_cnt - 1;
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end if;
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end if;
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end process mstimer;
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ms_tick <= '1' when ms_cnt = 0 else '0';
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ledcongen : for i in sig'low to sig'high generate
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ledblock : block
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constant LED_CNT_MAX : integer := 50; -- on time, in ms
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constant LED_CNT_MIN : integer := -50; -- off time, in ms
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signal led_cnt : integer range LED_CNT_MIN to LED_CNT_MAX;
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begin
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ledgen : if BLINK(i) generate
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ledproc : process(clk, rst) is
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begin
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if rst then
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led_cnt <= LED_CNT_MIN;
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elsif rising_edge(clk) then
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if (led_cnt = LED_CNT_MIN) then
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if sig(i) then
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led_cnt <= LED_CNT_MAX;
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end if;
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elsif ms_tick then
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led_cnt <= led_cnt - 1;
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end if;
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end if;
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end process ledproc;
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led_n(i) <= '0' when led_cnt > 0 else '1';
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else generate
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led_n(i) <= not sig(i);
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end generate ledgen;
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end block ledblock;
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end generate ledcongen;
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end architecture RTL;
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