78 lines
2.1 KiB
VHDL
78 lines
2.1 KiB
VHDL
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- cocotb_top_hwitl.vhd : Test bench for cocotb HW-in-the-loop tests
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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entity cocotb_top_hwitl is
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end entity cocotb_top_hwitl;
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architecture bench of cocotb_top_hwitl is
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-- DUT signals
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signal clk : std_logic;
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signal rst_n : std_logic;
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signal rx_p : std_logic;
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signal tx_p : std_logic;
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signal tx_n : std_logic;
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signal led_n : std_logic_vector(7 downto 0);
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signal button_n : std_logic_vector(3 downto 0);
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signal debug_data : std_logic_vector(7 downto 0);
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-- Generic test bench
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signal bench_ready : std_logic := '0';
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begin
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top_mac_test_inst : entity top_hwitl (mac) -- TODO: I haven't managed to get configurations working with cocotb yet, so changing this line changes the test case :(
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port map(
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clk => clk,
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rst_n => rst_n,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n,
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led_n => led_n,
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button_n => button_n,
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debug_data => debug_data
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);
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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rstsim : process is
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begin
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rst_n <= '0';
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wait for 400 ns;
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rst_n <= '1';
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wait for 100 ns;
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wait until rising_edge(clk);
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bench_ready <= '1';
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wait;
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end process rstsim;
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cocovc_eth_inst : entity work.cocovc_eth
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port map(
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rx_p => tx_p,
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rx_n => tx_n,
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tx_p => rx_p,
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tx_n => open
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);
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button_n <= (others => '1');
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end architecture bench;
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