trashernet/design/top_pingable.vhd

-- -------------------------------------------------------------------------- --
--               TRASHERNET - A Trashy Ethernet Stack for FPGAs               --
-- -------------------------------------------------------------------------- --
-- top_mac_test.vhd: Test design to verify the functionality of the MAC core
--   Sends a broadcast with 100 decrementing numbers every 250 ms or when a
--   button is pushed. It will also directly reply with that content to any
--   packet addressed to us.
--
--   Target: Lattice Brevia 2 (LFXP2-5E)
-- -------------------------------------------------------------------------- --
-- Author       : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License      : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use ieee.math_real.all;

library trashernet;
use trashernet.trashernet_pkg.all;

entity top_pingable is
	port(
		clk        : in  std_logic;
		rst_n      : in  std_logic;
		rx_p       : in  std_logic;
		tx_p       : out std_logic;
		tx_n       : out std_logic;
		led_n      : out std_logic_vector(7 downto 0);
		button_n   : in  std_logic_vector(3 downto 0);
		debug_data : out std_logic_vector(7 downto 0)
	);
end entity top_pingable;

architecture rtl of top_pingable is
	component pll0
		port(
			CLK   : in  std_logic;
			CLKOP : out std_logic;
			LOCK  : out std_logic
		);
	end component pll0;

	constant F_CLK     : integer := 50000000;
	constant F_CLK_PHY : integer := 140000000;

	constant LED_BLINK : boolean_vector(led_n'range) := (
		6 downto 2 => true,
		others     => false
	);

	constant ETH_CONFIG : configuration_t      := (
		mac_address => (x"00", x"FF", x"FF", x"11", x"22", x"44")
	);
	constant IP_CONFIG  : ipv4_configuration_t := (
		ip_address  => (x"C0", x"A8", x"02", x"02"),
		subnet_mask => (x"FF", x"FF", x"FF", x"00"),
		gateway     => (x"C0", x"A8", x"02", x"01")
	);

	signal rst          : std_logic;
	signal clk_phy      : std_logic;
	signal phy_pll_lock : std_logic;

	signal led_sig : std_logic_vector(led_n'range);

	signal phy_out : phy_out_t;
	signal phy_in  : phy_in_t;

	signal mac_out : mac_out_t;
	signal mac_in  : mac_in_t;

	constant PROT_ARP              : integer                     := 0;
	constant PROT_IPV4             : integer                     := 1;
	constant ETHERNET_II_PROTOCOLS : ethernet_ii_protocol_vector := (
		PROT_ARP  => ETHERNET_II_PROTOCOL_ARP,
		PROT_IPV4 => ETHERNET_II_PROTOCOL_IPV4
	);
	signal ethernet_i_out          : ethernet_i_out_t;
	signal ethernet_i_in           : ethernet_i_in_t;
	signal ethernet_ii_out         : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
	signal ethernet_ii_in          : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);

	signal arp_out : arp_out_t;
	signal arp_in  : arp_in_t;

	signal ipv4_out : ipv4_out_t;
	signal ipv4_in  : ipv4_in_t;

	constant IPROT_ICMP      : integer              := 0;
	constant IPV4_PROTOCOLS  : ipv4_protocol_vector := (
		IPROT_ICMP => IPV4_PROTOCOL_ICMP
	);
	signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
	signal ipv4_protocol_in  : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);

	signal button_n_sync : std_logic_vector(button_n'range);
	signal button        : std_logic_vector(button_n'range);
begin
	trashernet_icmp_inst : entity trashernet.trashernet_icmp
		port map(
			clk               => clk,
			rst               => rst,
			ipv4_protocol_out => ipv4_protocol_out(IPROT_ICMP),
			ipv4_protocol_in  => ipv4_protocol_in(IPROT_ICMP)
		);

	trashernet_ipv4prot_inst : entity trashernet.trashernet_ipv4prot
		generic map(
			IPV4_PROTOCOLS => IPV4_PROTOCOLS
		)
		port map(
			clk               => clk,
			rst               => rst,
			ipv4_out          => ipv4_out,
			ipv4_in           => ipv4_in,
			ipv4_protocol_out => ipv4_protocol_out,
			ipv4_protocol_in  => ipv4_protocol_in
		);

	trashernet_ipv4_inst : entity trashernet.trashernet_ipv4
		port map(
			clk             => clk,
			rst             => rst,
			ipv4_config     => IP_CONFIG,
			arp_out         => arp_out,
			arp_in          => arp_in,
			ethernet_ii_out => ethernet_ii_out(PROT_IPV4),
			ethernet_ii_in  => ethernet_ii_in(PROT_IPV4),
			ipv4_out        => ipv4_out,
			ipv4_in         => ipv4_in
		);

	trashernet_arp_inst : entity trashernet.trashernet_arp
		generic map(
			SYSTICK_FREQ => F_CLK
		)
		port map(
			clk             => clk,
			rst             => rst,
			systick         => '1',
			mac_config      => ETH_CONFIG,
			ip_config       => IP_CONFIG,
			arp_out         => arp_out,
			arp_in          => arp_in,
			ethernet_ii_out => ethernet_ii_out(PROT_ARP),
			ethernet_ii_in  => ethernet_ii_in(PROT_ARP)
		);

	ethernet_i_in <= ETHERNET_I_IN_UNUSED;

	trashernet_eth_inst : entity trashernet.trashernet_eth
		generic map(
			ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
		)
		port map(
			clk             => clk,
			rst             => rst,
			mac_out         => mac_out,
			mac_in          => mac_in,
			config          => ETH_CONFIG,
			ethernet_i_out  => ethernet_i_out,
			ethernet_i_in   => ethernet_i_in,
			ethernet_ii_out => ethernet_ii_out,
			ethernet_ii_in  => ethernet_ii_in
		);

	trashernet_mac_inst : entity trashernet.trashernet_mac
		port map(
			clk     => clk,
			rst     => rst,
			phy_out => phy_out,
			phy_in  => phy_in,
			mac_out => mac_out,
			mac_in  => mac_in
		);

	pll0_inst : pll0
		port map(
			CLK   => clk,
			CLKOP => clk_phy,
			LOCK  => phy_pll_lock
		);

	trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
		generic map(
			F_CLK     => F_CLK,
			F_CLK_PHY => F_CLK_PHY
		)
		port map(
			clk     => clk,
			phy_clk => clk_phy,
			rst     => rst,
			phy_out => phy_out,
			phy_in  => phy_in,
			rx_p    => rx_p,
			tx_p    => tx_p,
			tx_n    => tx_n
		);

	reset_sync : process(clk, rst_n) is
	begin
		if (rst_n = '0') then
			rst <= '1';
		elsif (rising_edge(clk)) then
			rst <= '0';
		end if;
	end process reset_sync;

	ledcon_inst : entity work.ledcon
		generic map(
			F_CLK => F_CLK,
			BLINK => LED_BLINK
		)
		port map(
			clk   => clk,
			rst   => rst,
			sig   => led_sig,
			led_n => led_n
		);

	led_sig <= (
		0 => phy_pll_lock,
		1 => phy_out.carrier_detect,
		2 => phy_out.rx_active,
		3 => phy_out.rx_error,
		4 => mac_out.rx_mac_crc_ok,
		5 => mac_out.rx_mac_crc_error,
		6 => mac_out.tx_active,
		7 => '0'
	);

	synchronizer_inst : entity trashernet.synchronizer
		generic map(
			SIZE => 2
		)
		port map(
			clk      => clk,
			rst      => rst,
			data_in  => button_n(0),
			data_out => button_n_sync(0)
		);

	button <= not button_n_sync;
end architecture rtl;