phy_cdc: Allow unlimited clock ratios
Actually, assuming that each clock domain is fast enough for 10 MBit/s, there is no problem running crazy ratios.
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@ -47,8 +47,6 @@ architecture rtl of trashernet_phy_cdc is
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signal rx_data_i : byte;
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signal rx_data_i : byte;
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begin
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begin
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assert F_CLK_PHY > 2 * F_CLK report "F_CLK_PHY must be at least 2x F_CLK" severity failure;
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-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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-- Drives: PHY clock domain
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-- Drives: PHY clock domain
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-- -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------
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