rmii: Do not prepend sync header
This is done by the MAC.
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3c592dbd23
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@ -182,7 +182,7 @@ begin
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signal temp_tx_data_en : std_logic;
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signal temp_tx_data_ack : std_logic;
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type state_t is (IDLE, HEADER, DATA, IPG);
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type state_t is (IDLE, DATA, IPG);
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signal state : state_t;
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signal sr : byte;
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signal dibit_cnt : integer range 0 to 3;
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@ -250,25 +250,14 @@ begin
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if byte_done then
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if byte_cnt > 0 then
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byte_cnt <= byte_cnt - 1;
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else
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end if;
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end if;
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case state is
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when IDLE =>
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sr <= x"55";
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byte_cnt <= SYNC_HEADER_SIZE_BYTES - 1;
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sr <= temp_tx_data;
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dibit_cnt <= 0;
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if temp_tx_data_en then
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state <= HEADER;
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end if;
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when HEADER =>
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sr <= x"55";
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if not temp_tx_data_en then
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state <= IDLE;
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elsif block_done then
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sr <= x"D5";
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state <= DATA;
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end if;
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@ -291,10 +280,10 @@ begin
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byte_done <= '1' when dibit_cnt = 3 else '0';
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block_done <= '1' when (byte_cnt = 0) and (byte_done = '1') else '0';
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temp_tx_data_ack <= '1' when (state = DATA) and (byte_done = '1') and (temp_tx_data_en = '1') else '0';
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phy_out.tx_active <= '1' when (state = HEADER) or (state = DATA) else '0';
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phy_out.tx_active <= '1' when state = DATA else '0';
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rmii_txd <= sr(1 downto 0);
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rmii_tx_en <= '1' when (state = HEADER) or (state = DATA) else '0';
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rmii_tx_en <= '1' when state = DATA else '0';
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end block transmitter;
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end architecture rtl;
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