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No commits in common. "1c281bc0f7601f668f6381c659dba7d33ebf565e" and "f224aee48730b22e12f68f299c6a769a8d1f1ff3" have entirely different histories.

3 changed files with 2 additions and 81 deletions

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@ -1,9 +1,7 @@
# defaults # defaults
SIM ?= ghdl SIM ?= ghdl
TOPLEVEL_LANG ?= vhdl TOPLEVEL_LANG ?= vhdl
BASE = $(PWD)/.. BASE = $(PWD)/..
BENCHTOP ?= cocotb_top_mac_test
COMPILE_ARGS=--std=08 COMPILE_ARGS=--std=08
SIM_ARGS ?= --wave=wave.ghw SIM_ARGS ?= --wave=wave.ghw
@ -13,7 +11,7 @@ VHDL_SOURCES_design += $(BASE)/design/*.vhd
VHDL_SOURCES_design += $(BASE)/bench/pll0.vhd VHDL_SOURCES_design += $(BASE)/bench/pll0.vhd
VHDL_SOURCES += $(BASE)/cocotb/*.vhd VHDL_SOURCES += $(BASE)/cocotb/*.vhd
TOPLEVEL ?= $(BENCHTOP) TOPLEVEL = cocotb_top_mac_test
MODULE ?= $(BENCHTOP) MODULE = cocotb_top_mac_test
include $(shell cocotb-config --makefiles)/Makefile.sim include $(shell cocotb-config --makefiles)/Makefile.sim

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@ -1,72 +0,0 @@
#!/usr/bin/env python
import cocotb
from cocotb.triggers import *
from cocotb.result import *
from cocotb.queue import Queue
from cocotb_helpers import buffers
import sys
import threading
import socket
import time
import os
import asyncio
import fcntl
class MacDevReceiver():
def __init__(self, dut, eth_tx, eth_rx, dev):
self.dut = dut
self.eth_tx = eth_tx
self.eth_rx = eth_rx
self.dev = dev
self.mac_rx_ev = Event()
print("Setting IF to promisc mode...")
os.system("ip link set promisc on dev {}".format(dev))
ETH_P_ALL=3
self.macdev=socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(ETH_P_ALL))
self.macdev.bind((dev, 0))
fcntl.fcntl(self.macdev, fcntl.F_SETFL, os.O_NONBLOCK)
async def main(self):
ETH_HEAD = b'\x55\x55\x55\x55\xD5'
while True:
try:
r = self.macdev.recv(2000)
await self.eth_tx.send(ETH_HEAD + r);
except:
await Timer(1, "us")
pass
async def main_rx(self):
while True:
frame = await self.eth_rx.queue.get()
self.dut._log.info("RX Frame: " + str(frame))
self.macdev.send(frame)
async def start(self):
await cocotb.start(self.main())
await cocotb.start(self.main_rx())
@cocotb.test()
async def hwitl(dut):
"""Real-Ethernet-hardware in the loop test"""
# Start verification components
eth_tx = buffers.tx_buffer(dut, "cocovc_eth_inst.cocotb_tx_")
await eth_tx.start()
eth_rx = buffers.rx_buffer(dut, "cocovc_eth_inst.cocotb_rx_")
await eth_rx.start()
# Start local monitors
macdev_receiver = MacDevReceiver(dut, eth_tx, eth_rx, "virt0")
# Wait for VHDL part to be ready
await Edge(dut.bench_ready)
print("beep")
await macdev_receiver.start()
print("Press Ctrl+C to stop the test.")
await Timer(100, "sec")

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@ -1,5 +0,0 @@
#!/bin/bash
echo Hardware in the loop test
make TOPLEVEL=cocotb_top_mac_test MODULE=hw_itl