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2190f146a0
...
6de8d24537
@ -6,7 +6,6 @@ Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to c
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* Layer 1, Physical: `trashernet_phy`
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* Layer 1, Physical: `trashernet_phy`
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* Layer 2, Data link: `trashernet_mac`, `trashernet_eth`, `trashernet_arp`
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* Layer 2, Data link: `trashernet_mac`, `trashernet_eth`, `trashernet_arp`
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* Layer 3, Network: `trashernet_ipv4`, `trashernet_ipv4prot`, `trashernet_icmp`
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When writing it, the following were the main design philosophies:
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When writing it, the following were the main design philosophies:
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@ -1,68 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="pingable" device="LFXP2-5E-6TN144C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
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<Options def_top="trashernet.fifo" lib="work" top="top_pingable"/>
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<Source name="../ip/pll0.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="../../../design/ledcon.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="../../../trashernet/cdc_strobe.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/crc.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/synchronizer.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_eth.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_mac.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_phy.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_phy_cdc.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_pkg.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_arp.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../design/top_hwitl.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="../../../trashernet/timer.vhd" type="VHDL" type_short="VHDL">
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<Options/>
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</Source>
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<Source name="../../../design/top_pingable.vhd" type="VHDL" type_short="VHDL">
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<Options top_module="top_pingable"/>
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</Source>
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<Source name="../../../trashernet/fifo.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_icmp.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_ipv4.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="../../../trashernet/trashernet_ipv4prot.vhd" type="VHDL" type_short="VHDL">
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<Options lib="trashernet"/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="pingable.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="pingable1.sty"/>
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</BaliProject>
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@ -1,47 +0,0 @@
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BLOCK RESETPATHS ;
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BLOCK ASYNCPATHS ;
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LOCATE COMP "clk" SITE "21" ;
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LOCATE COMP "rst_n" SITE "19" ;
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LOCATE COMP "rx_p" SITE "94" ;
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LOCATE COMP "led_n[0]" SITE "37" ;
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LOCATE COMP "led_n[1]" SITE "38" ;
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LOCATE COMP "led_n[2]" SITE "39" ;
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LOCATE COMP "led_n[3]" SITE "40" ;
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LOCATE COMP "led_n[4]" SITE "43" ;
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LOCATE COMP "led_n[5]" SITE "44" ;
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LOCATE COMP "led_n[6]" SITE "45" ;
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LOCATE COMP "led_n[7]" SITE "46" ;
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IOBUF PORT "rx_p" IO_TYPE=LVPECL33 ;
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IOBUF PORT "clk" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "rst_n" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[0]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[1]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[2]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[3]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[4]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[5]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[6]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "debug_data[7]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[0]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[1]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[2]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[3]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[4]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[5]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[6]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "led_n[7]" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "tx_n" IO_TYPE=LVCMOS33 ;
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IOBUF PORT "tx_p" IO_TYPE=LVCMOS33 ;
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LOCATE COMP "tx_n" SITE "114" ;
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LOCATE COMP "tx_p" SITE "116" ;
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LOCATE COMP "button_n[0]" SITE "54" ;
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LOCATE COMP "debug_data[0]" SITE "73" ;
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LOCATE COMP "debug_data[1]" SITE "74" ;
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LOCATE COMP "debug_data[2]" SITE "77" ;
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LOCATE COMP "debug_data[3]" SITE "87" ;
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LOCATE COMP "debug_data[4]" SITE "88" ;
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LOCATE COMP "debug_data[5]" SITE "89" ;
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LOCATE COMP "debug_data[6]" SITE "90" ;
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LOCATE COMP "debug_data[7]" SITE "91" ;
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BLOCK PATH FROM CLKNET "clk_c" TO CLKNET "clk_phy" ;
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BLOCK PATH FROM CLKNET "clk_phy" TO CLKNET "clk_c" ;
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@ -1,206 +0,0 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE strategy>
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<Strategy version="1.0" predefined="0" description="" label="Strategy1">
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<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
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<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
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<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
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<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
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<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
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<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
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<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
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<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
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<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
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<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
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<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
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<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
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<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
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<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
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<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
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<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
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<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
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<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
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<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
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<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
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<Property name="PROP_BIT_OutFormatBitGen_REF" value="Bit File (Binary)" time="0"/>
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<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
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<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
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<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
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<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
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<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
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<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
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<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
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<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
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<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
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<Property name="PROP_BIT_UFMOrder" value="Normal" time="0"/>
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<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
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<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
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<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
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<Property name="PROP_LST_CarryChain" value="True" time="0"/>
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<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
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<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
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<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
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<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
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<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
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<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
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<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
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<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
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<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
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<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
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<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
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<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
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<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
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<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_ForceGSRInfer" value="No" time="0"/>
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<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
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<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
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<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
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<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
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<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_NumCriticalPaths" value="" time="0"/>
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<Property name="PROP_LST_OptimizeGoal" value="Timing" time="0"/>
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<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
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<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
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||||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
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<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
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<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
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<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
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<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
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||||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
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<Property name="PROP_LST_VHDL2008" value="True" time="0"/>
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<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
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||||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
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|
||||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
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|
||||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
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|
||||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
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|
||||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
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|
||||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAP_PackLogMapDes" value="" time="0"/>
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|
||||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
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|
||||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
|
||||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
|
||||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
|
||||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
|
||||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
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|
||||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
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|
||||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
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|
||||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
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|
||||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
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|
||||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
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|
||||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
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|
||||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
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|
||||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
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|
||||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
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|
||||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
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|
||||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
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|
||||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
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|
||||||
<Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/>
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|
||||||
<Property name="PROP_PAR_RoutingCDR" value="1" time="0"/>
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|
||||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
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|
||||||
<Property name="PROP_PAR_RunTimeReduction" value="True" time="0"/>
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|
||||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
|
||||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
|
||||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
|
||||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynComArea" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
|
||||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
|
||||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
|
||||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
|
||||||
<Property name="PROP_SYN_DisableRegisterRep" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfArea" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfFrequency" value="200" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
|
||||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
|
||||||
<Property name="PROP_SYN_LibPath" value="" time="0"/>
|
|
||||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
|
||||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
|
||||||
<Property name="PROP_SYN_VHDL2008" value="True" time="0"/>
|
|
||||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
|
||||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
|
||||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
|
||||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
|
||||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
|
||||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
|
||||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
|
||||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
|
||||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
|
||||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
|
||||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
|
||||||
<Property name="PROP_TMCHK_EnableCheck" value="True" time="0"/>
|
|
||||||
</Strategy>
|
|
||||||
@ -1,248 +0,0 @@
|
|||||||
-- -------------------------------------------------------------------------- --
|
|
||||||
-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
|
|
||||||
-- -------------------------------------------------------------------------- --
|
|
||||||
-- top_mac_test.vhd: Test design to verify the functionality of the MAC core
|
|
||||||
-- Sends a broadcast with 100 decrementing numbers every 250 ms or when a
|
|
||||||
-- button is pushed. It will also directly reply with that content to any
|
|
||||||
-- packet addressed to us.
|
|
||||||
--
|
|
||||||
-- Target: Lattice Brevia 2 (LFXP2-5E)
|
|
||||||
-- -------------------------------------------------------------------------- --
|
|
||||||
-- Author : Markus Koch <markus@notsyncing.net>
|
|
||||||
-- Contributors : None
|
|
||||||
-- License : Mozilla Public License (MPL) Version 2
|
|
||||||
-- -------------------------------------------------------------------------- --
|
|
||||||
|
|
||||||
library ieee;
|
|
||||||
use ieee.std_logic_1164.all;
|
|
||||||
use ieee.numeric_std.all;
|
|
||||||
|
|
||||||
use ieee.math_real.all;
|
|
||||||
|
|
||||||
library trashernet;
|
|
||||||
use trashernet.trashernet_pkg.all;
|
|
||||||
|
|
||||||
entity top_pingable is
|
|
||||||
port(
|
|
||||||
clk : in std_logic;
|
|
||||||
rst_n : in std_logic;
|
|
||||||
rx_p : in std_logic;
|
|
||||||
tx_p : out std_logic;
|
|
||||||
tx_n : out std_logic;
|
|
||||||
led_n : out std_logic_vector(7 downto 0);
|
|
||||||
button_n : in std_logic_vector(3 downto 0);
|
|
||||||
debug_data : out std_logic_vector(7 downto 0)
|
|
||||||
);
|
|
||||||
end entity top_pingable;
|
|
||||||
|
|
||||||
architecture rtl of top_pingable is
|
|
||||||
component pll0
|
|
||||||
port(
|
|
||||||
CLK : in std_logic;
|
|
||||||
CLKOP : out std_logic;
|
|
||||||
LOCK : out std_logic
|
|
||||||
);
|
|
||||||
end component pll0;
|
|
||||||
|
|
||||||
constant F_CLK : integer := 50000000;
|
|
||||||
constant F_CLK_PHY : integer := 140000000;
|
|
||||||
|
|
||||||
constant LED_BLINK : boolean_vector(led_n'range) := (
|
|
||||||
6 downto 2 => true,
|
|
||||||
others => false
|
|
||||||
);
|
|
||||||
|
|
||||||
constant ETH_CONFIG : configuration_t := (
|
|
||||||
mac_address => (x"00", x"FF", x"FF", x"11", x"22", x"44")
|
|
||||||
);
|
|
||||||
constant IP_CONFIG : ipv4_configuration_t := (
|
|
||||||
ip_address => (x"C0", x"A8", x"02", x"02"),
|
|
||||||
subnet_mask => (x"FF", x"FF", x"FF", x"00"),
|
|
||||||
gateway => (x"C0", x"A8", x"02", x"01")
|
|
||||||
);
|
|
||||||
|
|
||||||
signal rst : std_logic;
|
|
||||||
signal clk_phy : std_logic;
|
|
||||||
signal phy_pll_lock : std_logic;
|
|
||||||
|
|
||||||
signal led_sig : std_logic_vector(led_n'range);
|
|
||||||
|
|
||||||
signal phy_out : phy_out_t;
|
|
||||||
signal phy_in : phy_in_t;
|
|
||||||
|
|
||||||
signal mac_out : mac_out_t;
|
|
||||||
signal mac_in : mac_in_t;
|
|
||||||
|
|
||||||
constant PROT_ARP : integer := 0;
|
|
||||||
constant PROT_IPV4 : integer := 1;
|
|
||||||
constant ETHERNET_II_PROTOCOLS : ethernet_ii_protocol_vector := (
|
|
||||||
PROT_ARP => ETHERNET_II_PROTOCOL_ARP,
|
|
||||||
PROT_IPV4 => ETHERNET_II_PROTOCOL_IPV4
|
|
||||||
);
|
|
||||||
signal ethernet_i_out : ethernet_i_out_t;
|
|
||||||
signal ethernet_i_in : ethernet_i_in_t;
|
|
||||||
signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
|
|
||||||
signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);
|
|
||||||
|
|
||||||
signal arp_out : arp_out_t;
|
|
||||||
signal arp_in : arp_in_t;
|
|
||||||
|
|
||||||
signal ipv4_out : ipv4_out_t;
|
|
||||||
signal ipv4_in : ipv4_in_t;
|
|
||||||
|
|
||||||
constant IPROT_ICMP : integer := 0;
|
|
||||||
constant IPV4_PROTOCOLS : ipv4_protocol_vector := (
|
|
||||||
IPROT_ICMP => IPV4_PROTOCOL_ICMP
|
|
||||||
);
|
|
||||||
signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
|
|
||||||
signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
|
|
||||||
|
|
||||||
signal button_n_sync : std_logic_vector(button_n'range);
|
|
||||||
signal button : std_logic_vector(button_n'range);
|
|
||||||
begin
|
|
||||||
trashernet_icmp_inst : entity trashernet.trashernet_icmp
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
ipv4_protocol_out => ipv4_protocol_out(IPROT_ICMP),
|
|
||||||
ipv4_protocol_in => ipv4_protocol_in(IPROT_ICMP)
|
|
||||||
);
|
|
||||||
|
|
||||||
trashernet_ipv4prot_inst : entity trashernet.trashernet_ipv4prot
|
|
||||||
generic map(
|
|
||||||
IPV4_PROTOCOLS => IPV4_PROTOCOLS
|
|
||||||
)
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
ipv4_out => ipv4_out,
|
|
||||||
ipv4_in => ipv4_in,
|
|
||||||
ipv4_protocol_out => ipv4_protocol_out,
|
|
||||||
ipv4_protocol_in => ipv4_protocol_in
|
|
||||||
);
|
|
||||||
|
|
||||||
trashernet_ipv4_inst : entity trashernet.trashernet_ipv4
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
ipv4_config => IP_CONFIG,
|
|
||||||
arp_out => arp_out,
|
|
||||||
arp_in => arp_in,
|
|
||||||
ethernet_ii_out => ethernet_ii_out(PROT_IPV4),
|
|
||||||
ethernet_ii_in => ethernet_ii_in(PROT_IPV4),
|
|
||||||
ipv4_out => ipv4_out,
|
|
||||||
ipv4_in => ipv4_in
|
|
||||||
);
|
|
||||||
|
|
||||||
trashernet_arp_inst : entity trashernet.trashernet_arp
|
|
||||||
generic map(
|
|
||||||
SYSTICK_FREQ => F_CLK
|
|
||||||
)
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
systick => '1',
|
|
||||||
mac_config => ETH_CONFIG,
|
|
||||||
ip_config => IP_CONFIG,
|
|
||||||
arp_out => arp_out,
|
|
||||||
arp_in => arp_in,
|
|
||||||
ethernet_ii_out => ethernet_ii_out(PROT_ARP),
|
|
||||||
ethernet_ii_in => ethernet_ii_in(PROT_ARP)
|
|
||||||
);
|
|
||||||
|
|
||||||
ethernet_i_in <= ETHERNET_I_IN_UNUSED;
|
|
||||||
|
|
||||||
trashernet_eth_inst : entity trashernet.trashernet_eth
|
|
||||||
generic map(
|
|
||||||
ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
|
|
||||||
)
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
mac_out => mac_out,
|
|
||||||
mac_in => mac_in,
|
|
||||||
config => ETH_CONFIG,
|
|
||||||
ethernet_i_out => ethernet_i_out,
|
|
||||||
ethernet_i_in => ethernet_i_in,
|
|
||||||
ethernet_ii_out => ethernet_ii_out,
|
|
||||||
ethernet_ii_in => ethernet_ii_in
|
|
||||||
);
|
|
||||||
|
|
||||||
trashernet_mac_inst : entity trashernet.trashernet_mac
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
phy_out => phy_out,
|
|
||||||
phy_in => phy_in,
|
|
||||||
mac_out => mac_out,
|
|
||||||
mac_in => mac_in
|
|
||||||
);
|
|
||||||
|
|
||||||
pll0_inst : pll0
|
|
||||||
port map(
|
|
||||||
CLK => clk,
|
|
||||||
CLKOP => clk_phy,
|
|
||||||
LOCK => phy_pll_lock
|
|
||||||
);
|
|
||||||
|
|
||||||
trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
|
|
||||||
generic map(
|
|
||||||
F_CLK => F_CLK,
|
|
||||||
F_CLK_PHY => F_CLK_PHY
|
|
||||||
)
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
phy_clk => clk_phy,
|
|
||||||
rst => rst,
|
|
||||||
phy_out => phy_out,
|
|
||||||
phy_in => phy_in,
|
|
||||||
rx_p => rx_p,
|
|
||||||
tx_p => tx_p,
|
|
||||||
tx_n => tx_n
|
|
||||||
);
|
|
||||||
|
|
||||||
reset_sync : process(clk, rst_n) is
|
|
||||||
begin
|
|
||||||
if (rst_n = '0') then
|
|
||||||
rst <= '1';
|
|
||||||
elsif (rising_edge(clk)) then
|
|
||||||
rst <= '0';
|
|
||||||
end if;
|
|
||||||
end process reset_sync;
|
|
||||||
|
|
||||||
ledcon_inst : entity work.ledcon
|
|
||||||
generic map(
|
|
||||||
F_CLK => F_CLK,
|
|
||||||
BLINK => LED_BLINK
|
|
||||||
)
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
sig => led_sig,
|
|
||||||
led_n => led_n
|
|
||||||
);
|
|
||||||
|
|
||||||
led_sig <= (
|
|
||||||
0 => phy_pll_lock,
|
|
||||||
1 => phy_out.carrier_detect,
|
|
||||||
2 => phy_out.rx_active,
|
|
||||||
3 => phy_out.rx_error,
|
|
||||||
4 => mac_out.rx_mac_crc_ok,
|
|
||||||
5 => mac_out.rx_mac_crc_error,
|
|
||||||
6 => mac_out.tx_active,
|
|
||||||
7 => '0'
|
|
||||||
);
|
|
||||||
|
|
||||||
synchronizer_inst : entity trashernet.synchronizer
|
|
||||||
generic map(
|
|
||||||
SIZE => 2
|
|
||||||
)
|
|
||||||
port map(
|
|
||||||
clk => clk,
|
|
||||||
rst => rst,
|
|
||||||
data_in => button_n(0),
|
|
||||||
data_out => button_n_sync(0)
|
|
||||||
);
|
|
||||||
|
|
||||||
button <= not button_n_sync;
|
|
||||||
end architecture rtl;
|
|
||||||
@ -143,28 +143,27 @@ begin
|
|||||||
|
|
||||||
signal full_length : ipv4_length;
|
signal full_length : ipv4_length;
|
||||||
|
|
||||||
signal sr : byte_vector(0 to 19);
|
|
||||||
signal byte_cnt : integer range 0 to sr'length - 1;
|
|
||||||
signal alt_byte : std_logic;
|
|
||||||
signal checksum : unsigned(20 downto 0); -- 20 Header fields -> 19 chances for carry -> 5 additional bits
|
|
||||||
signal checksum_ones : unsigned(15 downto 0);
|
|
||||||
|
|
||||||
constant TTL : byte := x"40";
|
constant TTL : byte := x"40";
|
||||||
impure function get_header(checksum : std_logic_vector(15 downto 0)) return byte_vector is
|
impure function get_header(checksum : std_logic_vector(15 downto 0)) return byte_vector is
|
||||||
variable ret : byte_vector(sr'range);
|
|
||||||
begin
|
begin
|
||||||
ret := --
|
return --
|
||||||
byte_vector'(
|
byte_vector'(
|
||||||
x"45", x"00", byte(full_length(15 downto 8)), byte(full_length(7 downto 0)), -- Ver/IHL, DSCP/ECN, Len
|
x"45", x"00", byte(full_length(15 downto 8)), byte(full_length(7 downto 0)), -- Ver/IHL, DSCP/ECN, Len
|
||||||
x"00", x"00", x"00", x"00" -- Identification, Flags/FragOffset
|
x"00", x"00", x"00", x"00" -- Identification, Flags/FragOffset
|
||||||
) & TTL & ipv4_in.tx_protocol & checksum(15 downto 8) & checksum(7 downto 0) & -- TTL, Protocol, Header Checksum
|
) & TTL & ipv4_in.tx_protocol & checksum(15 downto 8) & checksum(7 downto 0) & -- TTL, Protocol, Header Checksum
|
||||||
ipv4_config.ip_address & -- Source IP
|
ipv4_config.ip_address & -- Source IP
|
||||||
ipv4_in.tx_ip_address -- Destination IP
|
ipv4_in.tx_ip_address -- Destination IP
|
||||||
;
|
;
|
||||||
return ret;
|
|
||||||
end function get_header;
|
end function get_header;
|
||||||
|
|
||||||
|
constant PSEUDO_HEADER : byte_vector := get_header(x"0000");
|
||||||
|
signal sr : byte_vector(PSEUDO_HEADER'range);
|
||||||
|
signal byte_cnt : integer range 0 to sr'length - 1;
|
||||||
|
signal alt_byte : std_logic;
|
||||||
|
signal checksum : unsigned(20 downto 0); -- 20 Header fields -> 19 chances for carry -> 5 additional bits
|
||||||
|
signal checksum_ones : unsigned(15 downto 0);
|
||||||
begin
|
begin
|
||||||
full_length <= sr'length + ipv4_in.tx_length;
|
full_length <= PSEUDO_HEADER'length + ipv4_in.tx_length;
|
||||||
checksum_ones <= checksum(15 downto 0) + checksum(checksum'high downto 16);
|
checksum_ones <= checksum(15 downto 0) + checksum(checksum'high downto 16);
|
||||||
|
|
||||||
tx_fsm : process(clk, rst) is
|
tx_fsm : process(clk, rst) is
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user