fpga/trashernet
1
0
Fork 0
Code Issues 7 Pull Requests 2 Releases 2 Wiki Activity

Compare commits

base: fpga:37714d5c2da7f56aebd564b9149cf819562b5dde
Branches Tags
fpga:master
fpga:feature/trashernet-soc
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1
...
compare: fpga:afb545cd021961aee6f4d66259116d194454465e
Branches Tags
fpga:feature/trashernet-soc
fpga:master
fpga:feature/trashernet-as
fpga:fix/gateway
fpga:fix/prot_muxing
fpga:feature/ipv4
fpga:feature/arp
fpga:wip/cococi
fpga:v0.2
fpga:v0.1

5 Commits
37714d5c2d ... afb545cd02

Author SHA1 Message Date
Markus Koch
afb545cd02 Clean up code formatting 2022-01-22 20:50:18 +01:00
Markus Koch
4e39e3b371 phy: Do not report tx_active when providing NLPs 2022-01-22 20:48:49 +01:00
Markus Koch
a2edc540b2 phy: Fix NLP timebase error 2022-01-22 20:48:23 +01:00
Markus Koch
6f8bb7ba54 phy: Fix rounding error for NLP timeout 2022-01-22 20:47:47 +01:00
Markus Koch
76eaff20fd mac+phy: Initialize all required variables 2022-01-22 20:47:09 +01:00
3 changed files with 12 additions and 7 deletions
Show Stats Expand all files Collapse all files

5
trashernet/cdc_strobe.vhd
View File

@ -54,8 +54,7 @@ begin
);
-- strobify
b_toggle_last <= '0' when b_rst
else b_toggle when rising_edge(b_clk)
;
b_toggle_last <= '0' when b_rst else
b_toggle when rising_edge(b_clk);
b_out <= (b_toggle ?/= b_toggle_last);
end architecture rtl;

4
trashernet/trashernet_mac.vhd
View File

@ -79,6 +79,7 @@ begin
mac_out.rx_mac_crc_ok <= '0';
mac_out.rx_mac_header_rcv <= '0';
crc_clear <= '0';
state <= HEAD;
elsif rising_edge(clk) then
mac_out.rx_mac_valid <= '0';
@ -168,6 +169,9 @@ begin
begin
if rst then
mac_out.tx_mac_data_ack <= '0';
tx_state <= IDLE;
sr_cnt <= 0;
byte_cnt <= 0;
elsif rising_edge(clk) then
mac_out.tx_mac_data_ack <= '0';

10
trashernet/trashernet_phy.vhd
View File

@ -56,7 +56,7 @@ begin
signal bit_cnt : integer range 0 to 7;
-- NLP supervision
constant NLP_TIMEOUT_CNT_MAX : integer := integer(round(real(F_CLK) * 16.0 * 10.0**(-3))); -- Every 16 ms
constant NLP_TIMEOUT_CNT_MAX : integer := integer(round(real(F_CLK) * 16.0 * 10.0 ** (-3))); -- Every 16 ms
signal nlp_timeout_cnt : integer range 0 to NLP_TIMEOUT_CNT_MAX;
begin
-- Synchronize RX input
@ -260,7 +260,7 @@ begin
-- -------------------------------------------------------------------------
transmitter : block
constant TX_STB_CNT_MAX : integer := F_CLK / (F_ETH * 2) - 1;
constant TX_STB_CNT_MAX : integer := integer(round(real(F_CLK) / real((F_ETH * 2)))) - 1;
signal tx_stb_cnt : integer range 0 to TX_STB_CNT_MAX;
type tx_state_t is (IDLE, NLP, TX, IPG);
@ -268,7 +268,7 @@ begin
signal sr : std_logic_vector(phy_in.tx_data'range);
signal bit_stage : std_logic;
constant BIT_CNT_MAX_NLP : integer := 16000 / 100; -- 16 ms (timebase 100 ns)
constant BIT_CNT_MAX_NLP : integer := 16000000 / 100; -- 16 ms (timebase 100 ns)
constant BIT_CNT_MAX_IPG : integer := 96;
constant BIT_CNT_MAX_DATA : integer := sr'length - 1;
signal bit_cnt : integer range 0 to maximum(maximum(BIT_CNT_MAX_NLP, BIT_CNT_MAX_DATA), BIT_CNT_MAX_IPG);
@ -319,6 +319,8 @@ begin
phy_out.tx_data_ack <= '0';
tx_stb_cnt <= TX_STB_CNT_MAX;
tx_mode <= OFF;
tx_state <= IDLE;
bit_cnt <= 0;
go_idle;
elsif rising_edge(clk) then
@ -378,7 +380,7 @@ begin
end case;
end if;
end process tx_main;
phy_out.tx_active <= '1' when tx_state /= IDLE else '0';
phy_out.tx_active <= '1' when (tx_state /= IDLE and tx_state /= NLP) else '0';
driver : process(clk, rst) is
begin