trashernet/trashernet_phy.vhd

@@ -37,10 +37,9 @@ begin
 
 	receiver : block
 		-- Signal conditioning
-		signal rx             : std_logic;
+		signal rx      : std_logic;
-		signal rx_last        : std_logic;
+		signal rx_last : std_logic;
-		signal rx_last_static : std_logic;
+		signal rx_edge : std_logic;
-		signal rx_edge        : std_logic;
 
 		-- Bit recovery
 		signal bit_value : std_logic;
@@ -62,23 +61,11 @@ begin
 				data_out => rx
 			);
 
-		-- Edge detector for RX (+glitch filter)
+		-- Edge detector for RX
-		edgedet : process(clk, rst) is
+		rx_last <= '0' when rst
-		begin
+		           else rx when rising_edge(clk)
-			if rst then
+		         ;
-				rx_last        <= '0';
+		rx_edge <= rx_last xor rx;
-				rx_last_static <= '0';
-				rx_edge        <= '0';
-
-			elsif rising_edge(clk) then
-				rx_edge <= '0';
-				if (rx_last = rx) then
-					rx_edge        <= rx_last_static xor rx;
-					rx_last_static <= rx;
-				end if;
-				rx_last <= rx;
-			end if;
-		end process edgedet;
 
 		demanchestizer : block
 			-- Transition detector
@@ -98,7 +85,7 @@ begin
 			signal bit_ev          : bit_ev_t;
 
 			-- Bit recovery
-			type demanchestization_state_t is (SYNC, DATA, ERROR);
+			type demanchestization_state_t is (SYNC, DATA);
 			signal demanchestization_state : demanchestization_state_t;
 		begin
 			-- Detects spacing of transitions
@@ -146,7 +133,7 @@ begin
 
 					if transition_stb then
 						case last_transition is
-							when LONG => -- @suppress: Exit condition through indirect assignment
+							when LONG =>
 								if transition_duration = LONG then
 									bit_ev <= TOGGLE;
 								end if;
@@ -160,10 +147,6 @@ begin
 								last_transition <= LONG;
 						end case;
 					end if;
-
-					if (not transition_activity) then
-						last_transition <= LONG;
-					end if;
 				end if;
 			end process transition_analyzer;
 
@@ -174,32 +157,23 @@ begin
 					demanchestization_state <= SYNC;
 					bit_stb                 <= '0';
 					rx_active               <= '0';
-					rx_error                <= '0';
-				elsif rising_edge(clk) then
-					bit_stb  <= '0';
-					rx_error <= '0';
 
+				elsif rising_edge(clk) then
+					bit_stb <= '0';
 					if (bit_ev /= NONE) then
+						rx_active <= '1';
 						case demanchestization_state is
 							when SYNC =>
 								if (bit_ev = KEEP) then
 									bit_value               <= '1';
 									demanchestization_state <= DATA;
-									rx_active               <= '1';
 								end if;
-							when DATA => -- @suppress: Condition outside of case allows to exit this state
+							when DATA =>
 								bit_value <= not bit_value when bit_ev = TOGGLE else bit_value;
 								bit_stb   <= '1';
-							when ERROR => -- @suppress: Condition outside of case allows to exit this state
-								null;
 						end case;
 					end if;
 
-					if (bit_ev = ERROR) then
-						rx_error                <= '1';
-						demanchestization_state <= ERROR;
-					end if;
-
 					if (not transition_activity) then
 						demanchestization_state <= SYNC;
 						rx_active               <= '0';
@@ -220,7 +194,7 @@ begin
 
 				if rx_active then
 					if (bit_stb) then
-						data_rx <= bit_value & data_rx(data_rx'high downto data_rx'low + 1);
+						data_rx <= data_rx(data_rx'high - 1 downto 0) & bit_value;
 						if (bit_cnt = 7) then
 							data_rx_valid <= '1';
 							bit_cnt       <= 0;
@@ -238,7 +212,7 @@ begin
 		nlp_timeout_p : process(clk, rst) is
 		begin
 			if rst then
-				nlp_timeout_cnt <= 0;
+				nlp_timeout_cnt <= NLP_TIMEOUT_CNT_MAX;
 			elsif rising_edge(clk) then
 				if rx_edge then         -- Technically, we should use only the rising edge here, but a project called `trashernet` probably won't mind ;)
 					nlp_timeout_cnt <= NLP_TIMEOUT_CNT_MAX;
@@ -270,4 +244,5 @@ begin
 		end process nlp;
 		tx_p <= '1' when cnt < 0 else '0';
 	end block transmitter;
+
 end architecture rtl;