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8f4e996d57
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4b4e5fdbfa
@ -32,7 +32,7 @@ architecture bench of cocotb_top_hwitl is
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-- Generic test bench
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-- Generic test bench
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signal bench_ready : std_logic := '0';
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signal bench_ready : std_logic := '0';
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begin
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begin
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top_mac_test_inst : entity top_hwitl(eth) -- TODO: I haven't managed to get configurations working with cocotb yet, so changing this line changes the test case :(
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top_mac_test_inst : entity top_hwitl (mac) -- TODO: I haven't managed to get configurations working with cocotb yet, so changing this line changes the test case :(
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port map(
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port map(
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clk => clk,
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clk => clk,
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rst_n => rst_n,
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rst_n => rst_n,
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@ -44,6 +44,11 @@ architecture mac of top_hwitl is
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constant F_CLK : integer := 50000000;
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constant F_CLK : integer := 50000000;
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constant F_CLK_PHY : integer := 140000000;
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constant F_CLK_PHY : integer := 140000000;
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constant LED_BLINK : boolean_vector(led_n'range) := (
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6 downto 2 => true,
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others => false
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);
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constant ETH_CONFIG : configuration_t := (
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constant ETH_CONFIG : configuration_t := (
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mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
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mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
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);
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);
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@ -52,6 +57,8 @@ architecture mac of top_hwitl is
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signal clk_phy : std_logic;
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signal clk_phy : std_logic;
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signal phy_pll_lock : std_logic;
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signal phy_pll_lock : std_logic;
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signal led_sig : std_logic_vector(led_n'range);
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signal phy_out : phy_out_t;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal phy_in : phy_in_t;
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@ -63,6 +70,9 @@ architecture mac of top_hwitl is
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constant BYTE_CNT_MAX : integer := 100;
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constant BYTE_CNT_MAX : integer := 100;
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signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
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signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
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signal button_n_sync : std_logic_vector(button_n'range);
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signal button : std_logic_vector(button_n'range);
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constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1;
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constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1;
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signal tmo : integer range 0 to TMO_MAX;
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signal tmo : integer range 0 to TMO_MAX;
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begin
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begin
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@ -108,6 +118,42 @@ begin
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end if;
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end if;
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end process reset_sync;
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end process reset_sync;
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ledcon_inst : entity work.ledcon
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generic map(
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F_CLK => F_CLK,
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BLINK => LED_BLINK
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)
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port map(
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clk => clk,
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rst => rst,
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sig => led_sig,
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led_n => led_n
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);
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led_sig <= (
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0 => phy_pll_lock,
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1 => phy_out.carrier_detect,
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2 => phy_out.rx_active,
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3 => phy_out.rx_error,
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4 => mac_out.rx_mac_crc_ok,
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5 => mac_out.rx_mac_crc_error,
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6 => mac_out.tx_active,
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7 => '0'
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);
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synchronizer_inst : entity trashernet.synchronizer
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generic map(
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SIZE => 2
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)
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port map(
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clk => clk,
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rst => rst,
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data_in => button_n(0),
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data_out => button_n_sync(0)
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);
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button <= not button_n_sync;
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receiver : process(clk, rst) is
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receiver : process(clk, rst) is
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begin
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begin
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if rst then
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if rst then
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@ -128,7 +174,7 @@ begin
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end if;
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end if;
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end if;
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end if;
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if tmo = 0 then
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if (tmo = 0) or (button(0) = '1') then
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state <= TX;
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state <= TX;
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byte_cnt <= BYTE_CNT_MAX;
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byte_cnt <= BYTE_CNT_MAX;
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mac_in.tx_header.mac_destination <= (others => x"FF");
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mac_in.tx_header.mac_destination <= (others => x"FF");
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@ -157,127 +203,3 @@ begin
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debug_data(1) <= tx_n;
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debug_data(1) <= tx_n;
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end architecture mac;
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end architecture mac;
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-- -------------------------------------------------------------------------- --
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-- top_hwitl (eth)
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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architecture eth of top_hwitl is
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component pll0
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port(
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CLK : in std_logic;
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CLKOP : out std_logic;
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LOCK : out std_logic
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);
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end component pll0;
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constant F_CLK : integer := 50000000;
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constant F_CLK_PHY : integer := 140000000;
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constant ETH_CONFIG : configuration_t := (
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mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
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);
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signal rst : std_logic;
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signal clk_phy : std_logic;
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signal phy_pll_lock : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal mac_out : mac_out_t;
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signal mac_in : mac_in_t;
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constant PROT_ARP : integer := 0;
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constant PROT_IP : integer := 1;
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constant ETHERNET_II_PROTOCOLS : ethernet_ii_protocol_vector := (PROT_ARP => ETHERNET_II_PROTOCOL_ARP, PROT_IP => ETHERNET_II_PROTOCOL_IP);
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signal ethernet_i_out : ethernet_i_out_t;
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signal ethernet_i_in : ethernet_i_in_t;
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signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);
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begin
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trashernet_eth_inst : entity trashernet.trashernet_eth
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generic map(
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ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
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)
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port map(
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clk => clk,
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rst => rst,
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mac_out => mac_out,
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mac_in => mac_in,
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config => ETH_CONFIG,
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ethernet_i_out => ethernet_i_out,
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ethernet_i_in => ethernet_i_in,
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ethernet_ii_out => ethernet_ii_out,
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ethernet_ii_in => ethernet_ii_in
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);
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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mac_out => mac_out,
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mac_in => mac_in
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);
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pll0_inst : pll0
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port map(
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CLK => clk,
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CLKOP => clk_phy,
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LOCK => phy_pll_lock
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);
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => F_CLK,
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F_CLK_PHY => F_CLK_PHY
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)
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port map(
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clk => clk,
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phy_clk => clk_phy,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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reset_sync : process(clk, rst_n) is
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begin
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if (rst_n = '0') then
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rst <= '1';
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elsif (rising_edge(clk)) then
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rst <= '0';
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end if;
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end process reset_sync;
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receiver : process(clk, rst) is
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begin
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if rst then
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elsif rising_edge(clk) then
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if ethernet_i_out.rx_header_rcv then
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report "RX ETH-I: " & to_string(to_integer(ethernet_i_out.rx_length));
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end if;
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if (ethernet_ii_out(PROT_ARP).rx_header_rcv) then
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report "RX ARP";
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end if;
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if (ethernet_ii_out(PROT_IP).rx_header_rcv) then
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report "RX IP";
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end if;
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end if;
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end process receiver;
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end architecture eth;
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@ -52,6 +52,10 @@ architecture rtl of top_mac_test is
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others => false
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others => false
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);
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);
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type configuration_t is record
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mac_address : mac_addr_t;
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end record configuration_t;
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constant ETH_CONFIG : configuration_t := (
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constant ETH_CONFIG : configuration_t := (
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mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
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mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
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);
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);
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@ -1,170 +0,0 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- trashernet_eth.vhd : Ethernet OSI Layer 2, Data Link, ETH I/II Ethertype
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-- Implements arbitration of different ethertypes.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
|
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.trashernet_pkg.all;
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entity trashernet_eth is
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generic(
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ETHERNET_II_PROTOCOLS : ethernet_ii_protocol_vector := ETHERNET_II_PROTOCOLS_NONE
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);
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port(
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-- Global
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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-- MAC application interface
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mac_out : in mac_out_t; -- MAC application IF (out of MAC)
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mac_in : out mac_in_t; -- MAC application IF (into MAC)
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|
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-- Configuration
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config : in configuration_t; -- Global Trashernet configuration
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-- Ethernet 802.3 application interface
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ethernet_i_out : out ethernet_i_out_t; -- Ethernet 802.3 IF (out from MAC)
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ethernet_i_in : in ethernet_i_in_t := ETHERNET_I_IN_UNUSED; -- Ethernet 802.3 IF (out from MAC)
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-- Ethernet II application interface
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ethernet_ii_out : out ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range); -- Ethernet II IF (out from MAC)
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ethernet_ii_in : in ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range) := (others => ETHERNET_II_IN_UNUSED) -- Ethernet II IF (into MAC)
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);
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end entity trashernet_eth;
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architecture rtl of trashernet_eth is
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signal tx_data_ack_ii : std_logic_vector(ethernet_ii_out'range);
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signal tx_data_ack_i : std_logic;
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begin
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rx : block
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constant SEL_ETH_I : integer := ethernet_ii_out'low - 1;
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|
||||||
constant SEL_ETH_NONE : integer := ethernet_ii_out'low - 2;
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signal sel : integer range SEL_ETH_NONE to ethernet_ii_out'high;
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signal mac_destination_matches : std_logic;
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signal rx_mac_header_rcv_delayed : std_logic;
|
|
||||||
|
|
||||||
begin
|
|
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mac_destination_matches <= '1' when --
|
|
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((mac_out.rx_header.mac_destination = (x"FF", x"FF", x"FF", x"FF", x"FF", x"FF")) or --
|
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(mac_out.rx_header.mac_destination = config.mac_address)) else
|
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'0';
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|
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mux : process(clk, rst) is
|
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begin
|
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if rst then
|
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sel <= SEL_ETH_NONE;
|
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rx_mac_header_rcv_delayed <= '0';
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|
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elsif rising_edge(clk) then
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rx_mac_header_rcv_delayed <= mac_out.rx_mac_header_rcv;
|
|
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|
|
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if mac_out.rx_mac_header_rcv then
|
|
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sel <= SEL_ETH_NONE; -- By default, let's assume it's not for us
|
|
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if mac_destination_matches then
|
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||||||
if (unsigned(std_logic_vector'(mac_out.rx_header.mac_ethertype(0) & mac_out.rx_header.mac_ethertype(1))) < 1500) then -- Ethernet 802.3 Frame
|
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sel <= SEL_ETH_I;
|
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||||||
|
|
||||||
else -- Ethernet II Frame
|
|
||||||
for i in ETHERNET_II_PROTOCOLS'range loop
|
|
||||||
if (mac_out.rx_header.mac_ethertype = ETHERNET_II_PROTOCOLS(i).ethertype) then
|
|
||||||
sel <= i;
|
|
||||||
end if;
|
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||||||
end loop;
|
|
||||||
end if;
|
|
||||||
end if;
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|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
end process mux;
|
|
||||||
|
|
||||||
-- Shared fields in the Ethernet II application interface
|
|
||||||
shared_fields : for i in ethernet_ii_out'range generate
|
|
||||||
ethernet_ii_out(i).rx_mac_address <= mac_out.rx_header.mac_source;
|
|
||||||
ethernet_ii_out(i).rx_data <= mac_out.rx_mac_data;
|
|
||||||
ethernet_ii_out(i).rx_data_valid <= mac_out.rx_mac_valid when sel = i else '0';
|
|
||||||
ethernet_ii_out(i).rx_crc_error <= mac_out.rx_mac_crc_error when sel = i else '0';
|
|
||||||
ethernet_ii_out(i).rx_crc_ok <= mac_out.rx_mac_crc_ok when sel = i else '0';
|
|
||||||
ethernet_ii_out(i).rx_header_rcv <= rx_mac_header_rcv_delayed when sel = i else '0';
|
|
||||||
end generate shared_fields;
|
|
||||||
|
|
||||||
-- Shared fields in the Ethernet application interface
|
|
||||||
ethernet_i_out.rx_data <= mac_out.rx_mac_data;
|
|
||||||
ethernet_i_out.rx_data_valid <= mac_out.rx_mac_valid when sel = SEL_ETH_I;
|
|
||||||
ethernet_i_out.rx_crc_error <= mac_out.rx_mac_crc_error when sel = SEL_ETH_I else '0';
|
|
||||||
ethernet_i_out.rx_crc_ok <= mac_out.rx_mac_crc_ok when sel = SEL_ETH_I else '0';
|
|
||||||
ethernet_i_out.rx_header_rcv <= rx_mac_header_rcv_delayed when sel = SEL_ETH_I else '0';
|
|
||||||
ethernet_i_out.rx_mac_address <= mac_out.rx_header.mac_source;
|
|
||||||
ethernet_i_out.rx_length <= unsigned(mac_out.rx_header.mac_ethertype(0)) & unsigned(mac_out.rx_header.mac_ethertype(1));
|
|
||||||
|
|
||||||
-- TX fields (need to be driven here to avoid multiple drivers (blocks drive ALL signals of a record))
|
|
||||||
tx_fields : for i in ethernet_ii_out'range generate
|
|
||||||
ethernet_ii_out(i).tx_data_ack <= tx_data_ack_ii(i);
|
|
||||||
end generate;
|
|
||||||
ethernet_i_out.tx_data_ack <= tx_data_ack_i;
|
|
||||||
end block rx;
|
|
||||||
|
|
||||||
tx : block
|
|
||||||
type state_t is (IDLE, TXD);
|
|
||||||
signal state : state_t;
|
|
||||||
constant SEL_ETH_I : integer := ethernet_ii_out'low - 1;
|
|
||||||
signal sel : integer range SEL_ETH_I to ethernet_ii_in'high;
|
|
||||||
begin
|
|
||||||
arb : process(clk, rst) is
|
|
||||||
begin
|
|
||||||
if rst then
|
|
||||||
|
|
||||||
elsif rising_edge(clk) then
|
|
||||||
case state is
|
|
||||||
when IDLE =>
|
|
||||||
if mac_out.tx_active then
|
|
||||||
if (ethernet_i_in.tx_en) then -- ETH I has priority
|
|
||||||
sel <= SEL_ETH_I;
|
|
||||||
state <= TXD;
|
|
||||||
else
|
|
||||||
for i in ethernet_ii_in'range loop
|
|
||||||
if ethernet_ii_in(i).tx_en then
|
|
||||||
sel <= i;
|
|
||||||
state <= TXD;
|
|
||||||
exit; -- Prioritize according to vector
|
|
||||||
end if;
|
|
||||||
end loop;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
when TXD =>
|
|
||||||
state <= IDLE when (mac_in.tx_mac_data_en or mac_out.tx_active);
|
|
||||||
end case;
|
|
||||||
end if;
|
|
||||||
end process arb;
|
|
||||||
|
|
||||||
mux : process(all) is
|
|
||||||
begin
|
|
||||||
if (sel = SEL_ETH_I) then
|
|
||||||
mac_in.tx_mac_data_en <= ethernet_i_in.tx_en;
|
|
||||||
mac_in.tx_mac_data <= ethernet_i_in.tx_data;
|
|
||||||
tx_data_ack_i <= mac_out.tx_mac_data_ack;
|
|
||||||
mac_in.tx_header.mac_destination <= ethernet_i_in.tx_mac_address;
|
|
||||||
mac_in.tx_header.mac_ethertype <= byte(ethernet_i_in.tx_length(15 downto 8)) & byte(ethernet_i_in.tx_length(7 downto 0));
|
|
||||||
else
|
|
||||||
mac_in.tx_mac_data_en <= ethernet_ii_in(sel).tx_en;
|
|
||||||
mac_in.tx_mac_data <= ethernet_ii_in(sel).tx_data;
|
|
||||||
txack : for i in ethernet_ii_out'range loop
|
|
||||||
tx_data_ack_ii(i) <= mac_out.tx_mac_data_ack when sel = i else '0';
|
|
||||||
end loop txack;
|
|
||||||
|
|
||||||
mac_in.tx_header.mac_destination <= ethernet_ii_in(sel).tx_mac_address;
|
|
||||||
mac_in.tx_header.mac_ethertype <= ETHERNET_II_PROTOCOLS(sel).ethertype;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
mac_in.tx_header.mac_source <= config.mac_address;
|
|
||||||
end process mux;
|
|
||||||
end block tx;
|
|
||||||
end architecture rtl;
|
|
||||||
@ -10,7 +10,6 @@
|
|||||||
|
|
||||||
library ieee;
|
library ieee;
|
||||||
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
||||||
use ieee.numeric_std.all;
|
|
||||||
|
|
||||||
package trashernet_pkg is
|
package trashernet_pkg is
|
||||||
-- General types
|
-- General types
|
||||||
@ -30,11 +29,6 @@ package trashernet_pkg is
|
|||||||
-- IP specific types
|
-- IP specific types
|
||||||
subtype ip_addr_t is byte_vector(0 to 3);
|
subtype ip_addr_t is byte_vector(0 to 3);
|
||||||
|
|
||||||
-- Configuration interface
|
|
||||||
type configuration_t is record
|
|
||||||
mac_address : mac_addr_t; -- MAC address of this node
|
|
||||||
end record configuration_t;
|
|
||||||
|
|
||||||
-- PHY interface
|
-- PHY interface
|
||||||
type phy_in_t is record
|
type phy_in_t is record
|
||||||
tx_data : byte; -- TX Data
|
tx_data : byte; -- TX Data
|
||||||
@ -71,51 +65,6 @@ package trashernet_pkg is
|
|||||||
rx_mac_crc_error : std_logic; -- End of packet, CRC invalid
|
rx_mac_crc_error : std_logic; -- End of packet, CRC invalid
|
||||||
end record mac_out_t;
|
end record mac_out_t;
|
||||||
|
|
||||||
-- MAC ETH interface
|
|
||||||
type ethernet_ii_protocol_t is record
|
|
||||||
ethertype : ethertype_t;
|
|
||||||
end record;
|
|
||||||
type ethernet_ii_protocol_vector is array (natural range <>) of ethernet_ii_protocol_t;
|
|
||||||
constant ETHERNET_II_PROTOCOLS_NONE : ethernet_ii_protocol_vector(0 to -1) := (others => (ethertype => (x"00", x"00"))); -- NULL range
|
|
||||||
constant ETHERNET_II_PROTOCOL_IP : ethernet_ii_protocol_t := (ethertype => (x"08", x"00"));
|
|
||||||
constant ETHERNET_II_PROTOCOL_ARP : ethernet_ii_protocol_t := (ethertype => (x"08", x"06"));
|
|
||||||
|
|
||||||
type ethernet_i_out_t is record
|
|
||||||
rx_mac_address : mac_addr_t; -- Source MAC address
|
|
||||||
rx_crc_ok : std_logic; -- End of packet, CRC OK
|
|
||||||
rx_crc_error : std_logic; -- End of packet, CRC invalid
|
|
||||||
|
|
||||||
rx_data : byte; -- RX data
|
|
||||||
rx_data_valid : std_logic; -- RX data valid strobe
|
|
||||||
rx_length : unsigned(15 downto 0); -- RX payload length in bytes
|
|
||||||
rx_header_rcv : std_logic; -- Start of reception, `rx_length` is valid
|
|
||||||
tx_data_ack : std_logic; -- Give next data byte or disable `tx_en`
|
|
||||||
end record;
|
|
||||||
type ethernet_i_in_t is record
|
|
||||||
tx_mac_address : mac_addr_t; -- Destination MAC address
|
|
||||||
tx_data : byte; -- TX data
|
|
||||||
tx_en : std_logic; -- Start and continue transmitting
|
|
||||||
tx_length : unsigned(15 downto 0); -- TX payload length in bytes
|
|
||||||
end record;
|
|
||||||
constant ETHERNET_I_IN_UNUSED : ethernet_i_in_t := (tx_mac_address => (others => x"00"), tx_data => x"00", tx_length => x"0000", others => '0'); -- TODO
|
|
||||||
|
|
||||||
type ethernet_ii_out_t is record
|
|
||||||
rx_mac_address : mac_addr_t; -- Source MAC address
|
|
||||||
rx_data : byte; -- RX data
|
|
||||||
rx_data_valid : std_logic; -- RX data valid strobe
|
|
||||||
rx_crc_ok : std_logic; -- End of packet, CRC OK
|
|
||||||
rx_crc_error : std_logic; -- End of packet, CRC invalid
|
|
||||||
rx_header_rcv : std_logic; -- Start of reception
|
|
||||||
tx_data_ack : std_logic; -- Give next data byte or disable `tx_en`
|
|
||||||
end record;
|
|
||||||
type ethernet_ii_in_t is record
|
|
||||||
tx_mac_address : mac_addr_t; -- Destination MAC address
|
|
||||||
tx_data : byte; -- TX data
|
|
||||||
tx_en : std_logic; -- Start and continue transmitting
|
|
||||||
end record;
|
|
||||||
type ethernet_ii_out_vector is array (natural range <>) of ethernet_ii_out_t;
|
|
||||||
type ethernet_ii_in_vector is array (natural range <>) of ethernet_ii_in_t;
|
|
||||||
constant ETHERNET_II_IN_UNUSED : ethernet_ii_in_t := (tx_mac_address => (others => x"00"), tx_data => x"00", others => '0');
|
|
||||||
end package trashernet_pkg;
|
end package trashernet_pkg;
|
||||||
|
|
||||||
package body trashernet_pkg is
|
package body trashernet_pkg is
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user