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			f224aee487
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			1c281bc0f7
		
	
	| Author | SHA1 | Date | |
|---|---|---|---|
| 1c281bc0f7 | |||
| c4f4cfe68e | 
@ -1,7 +1,9 @@
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# defaults
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SIM ?= ghdl
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TOPLEVEL_LANG ?= vhdl
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BASE = $(PWD)/..
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BENCHTOP ?= cocotb_top_mac_test
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COMPILE_ARGS=--std=08
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SIM_ARGS ?= --wave=wave.ghw
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@ -11,7 +13,7 @@ VHDL_SOURCES_design += $(BASE)/design/*.vhd
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VHDL_SOURCES_design += $(BASE)/bench/pll0.vhd
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VHDL_SOURCES += $(BASE)/cocotb/*.vhd
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TOPLEVEL = cocotb_top_mac_test
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MODULE = cocotb_top_mac_test
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TOPLEVEL ?= $(BENCHTOP)
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MODULE ?= $(BENCHTOP)
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include $(shell cocotb-config --makefiles)/Makefile.sim
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										72
									
								
								cocotb/hw_itl.py
									
									
									
									
									
										Normal file
									
								
							
							
						
						
									
										72
									
								
								cocotb/hw_itl.py
									
									
									
									
									
										Normal file
									
								
							@ -0,0 +1,72 @@
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#!/usr/bin/env python
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import cocotb
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from cocotb.triggers import *
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from cocotb.result import *
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from cocotb.queue import Queue
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from cocotb_helpers import buffers
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import sys
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import threading
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import socket
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import time
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import os
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import asyncio
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import fcntl
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class MacDevReceiver():
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	def __init__(self, dut, eth_tx, eth_rx, dev):
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		self.dut = dut
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		self.eth_tx = eth_tx
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		self.eth_rx = eth_rx
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		self.dev = dev
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		self.mac_rx_ev = Event()
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		print("Setting IF to promisc mode...")
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		os.system("ip link set promisc on dev {}".format(dev))
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		ETH_P_ALL=3
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		self.macdev=socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(ETH_P_ALL))
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		self.macdev.bind((dev, 0))
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		fcntl.fcntl(self.macdev, fcntl.F_SETFL, os.O_NONBLOCK)
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	async def main(self):
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		ETH_HEAD = b'\x55\x55\x55\x55\xD5'
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		while True:
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			try:
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				r = self.macdev.recv(2000)
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				await self.eth_tx.send(ETH_HEAD + r);
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			except:
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				await Timer(1, "us")
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				pass
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	async def main_rx(self):
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		while True:
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			frame = await self.eth_rx.queue.get()
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			self.dut._log.info("RX Frame: " + str(frame))
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			self.macdev.send(frame)
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	async def start(self):
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		await cocotb.start(self.main())
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		await cocotb.start(self.main_rx())
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@cocotb.test()
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async def hwitl(dut):
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	"""Real-Ethernet-hardware in the loop test"""
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	# Start verification components
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	eth_tx = buffers.tx_buffer(dut, "cocovc_eth_inst.cocotb_tx_")
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	await eth_tx.start()
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	eth_rx = buffers.rx_buffer(dut, "cocovc_eth_inst.cocotb_rx_")
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	await eth_rx.start()
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	# Start local monitors
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	macdev_receiver = MacDevReceiver(dut, eth_tx, eth_rx, "virt0")
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	# Wait for VHDL part to be ready
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	await Edge(dut.bench_ready)
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	print("beep")
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	await macdev_receiver.start()
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	print("Press Ctrl+C to stop the test.")
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	await Timer(100, "sec")
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										5
									
								
								cocotb/hw_itl.sh
									
									
									
									
									
										Executable file
									
								
							
							
						
						
									
										5
									
								
								cocotb/hw_itl.sh
									
									
									
									
									
										Executable file
									
								
							@ -0,0 +1,5 @@
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#!/bin/bash
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echo Hardware in the loop test
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make TOPLEVEL=cocotb_top_mac_test MODULE=hw_itl
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