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@ -28,14 +28,6 @@ Notes:
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* The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
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* The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
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* On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D
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* On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D
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## Stats
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Sythesized for a Lattice LFXP2-5E FPGA using LSE / Diamond v3.12:
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| Configuration | Slices | LUT4 | Registers |
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| ---------------- | ------ | ---- | --------- |
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| `trashernet_phy` | 115 | 188 | 91 |
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## License
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## License
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This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.
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This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.
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@ -253,7 +253,6 @@ begin
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begin
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begin
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if rst then
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if rst then
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phy_out.rx_data_valid <= '0';
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phy_out.rx_data_valid <= '0';
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phy_out.rx_data <= (others => '0'); -- Needed for yosys to compile
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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phy_out.rx_data_valid <= '0';
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phy_out.rx_data_valid <= '0';
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@ -105,8 +105,6 @@ begin
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begin
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begin
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if rst then
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if rst then
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phy_out.rx_data_valid <= '0';
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phy_out.rx_data_valid <= '0';
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phy_out.rx_data <= (others => '0'); -- Needed for yosys to compile
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elsif rising_edge(clk) then
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elsif rising_edge(clk) then
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phy_out.rx_data_valid <= rx_data_valid_i;
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phy_out.rx_data_valid <= rx_data_valid_i;
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phy_out.rx_data <= phy_phy_out.rx_data; -- Data should be stable after the time it takes the _valid signal to go through the synchronizer
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phy_out.rx_data <= phy_phy_out.rx_data; -- Data should be stable after the time it takes the _valid signal to go through the synchronizer
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