Implement TCP Layer (listen) #16

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opened 2022-11-05 16:45:49 +01:00 by markus · 0 comments
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Some thoughts:

  • Create RX-RAM that holds <peer IP><peer port><rx seq>
  • Create TX-RAM that holds <tx seq>
  • One entity-port per handler (there can be multiple per network port), and a constant for each entity-port to link it to a real port
  • On RX start:
    • Loop through RX-RAM list and check if RxPort=ConfPort and whether the peer IP/port combo exists. Take that if matches or IP field 0.0.0.0 (i.e. empty slot, TBD: maybe we also need a signal to indicate the state of the connection...) as fallback
    • If in sequence, process further and prepare TX ACK
    • Then forward data to that application port
  • On TX start (or ACK requested):
    • Load TX-RAM to port index, get tx seq.
    • TBD: Check that slot is active
    • Transmit packet (possibly setting ACK with information, may be done as part of the data package)
    • Update tx seq
Some thoughts: * Create RX-RAM that holds `<peer IP><peer port><rx seq>` * Create TX-RAM that holds `<tx seq>` * One entity-port per handler (there can be multiple per network port), and a constant for each entity-port to link it to a real port * On RX start: * Loop through RX-RAM list and check if RxPort=ConfPort and whether the peer IP/port combo exists. Take that if matches or IP field 0.0.0.0 (i.e. empty slot, TBD: maybe we also need a signal to indicate the state of the connection...) as fallback * If in sequence, process further and prepare TX ACK * Then forward data to that application port * On TX start (or ACK requested): * Load TX-RAM to port index, get `tx seq`. * TBD: Check that slot is active * Transmit packet (possibly setting ACK with information, may be done as part of the data package) * Update tx seq
markus added the
feature
label 2022-11-05 16:45:49 +01:00
markus added this to the TCP <-> Serial Bridge milestone 2022-12-18 21:40:26 +01:00
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Reference: fpga/trashernet#16
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