113 lines
4.2 KiB
VHDL
113 lines
4.2 KiB
VHDL
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.0.240.2
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-- Module Version: 5.7
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--/usr/local/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth lse -arch mg5a00 -type pll -fin 50 -phase_cntl STATIC -fclkop 140 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2
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-- Sat Jan 22 20:39:11 2022
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- synopsys translate_off
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library xp2;
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use xp2.components.all;
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-- synopsys translate_on
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entity pll0 is
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port(
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CLK : in std_logic;
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CLKOP : out std_logic;
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LOCK : out std_logic);
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end pll0;
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architecture Structure of pll0 is
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-- internal signal declarations
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signal CLKOP_t : std_logic;
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signal scuba_vlo : std_logic;
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-- local component declarations
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component VLO
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port(Z : out std_logic);
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end component;
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component EPLLD1
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-- synopsys translate_off
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generic(CLKOK_BYPASS : in String; CLKOS_BYPASS : in String;
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CLKOP_BYPASS : in String; DUTY : in Integer;
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PHASEADJ : in String; PHASE_CNTL : in String;
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CLKOK_DIV : in Integer; CLKFB_DIV : in Integer;
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CLKOP_DIV : in Integer; CLKI_DIV : in Integer);
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-- synopsys translate_on
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port(CLKI : in std_logic; CLKFB : in std_logic; RST : in std_logic;
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RSTK : in std_logic; DPAMODE : in std_logic; DRPAI3 : in std_logic;
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DRPAI2 : in std_logic; DRPAI1 : in std_logic; DRPAI0 : in std_logic;
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DFPAI3 : in std_logic; DFPAI2 : in std_logic; DFPAI1 : in std_logic;
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DFPAI0 : in std_logic; PWD : in std_logic; CLKOP : out std_logic;
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CLKOS : out std_logic; CLKOK : out std_logic; LOCK : out std_logic;
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CLKINTFB : out std_logic);
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end component;
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attribute CLKOK_BYPASS : string;
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attribute CLKOS_BYPASS : string;
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attribute FREQUENCY_PIN_CLKOP : string;
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attribute CLKOP_BYPASS : string;
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attribute PHASE_CNTL : string;
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attribute DUTY : string;
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attribute PHASEADJ : string;
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attribute FREQUENCY_PIN_CLKI : string;
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attribute CLKOK_DIV : string;
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attribute CLKOP_DIV : string;
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attribute CLKFB_DIV : string;
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attribute CLKI_DIV : string;
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attribute FIN : string;
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attribute CLKOK_BYPASS of PLLInst_0 : label is "DISABLED";
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attribute CLKOS_BYPASS of PLLInst_0 : label is "DISABLED";
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attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "140.000000";
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attribute CLKOP_BYPASS of PLLInst_0 : label is "DISABLED";
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attribute PHASE_CNTL of PLLInst_0 : label is "STATIC";
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attribute DUTY of PLLInst_0 : label is "8";
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attribute PHASEADJ of PLLInst_0 : label is "0.0";
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attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "50.000000";
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attribute CLKOK_DIV of PLLInst_0 : label is "2";
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attribute CLKOP_DIV of PLLInst_0 : label is "4";
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attribute CLKFB_DIV of PLLInst_0 : label is "14";
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attribute CLKI_DIV of PLLInst_0 : label is "5";
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attribute FIN of PLLInst_0 : label is "50.000000";
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attribute syn_keep : boolean;
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attribute NGD_DRC_MASK : integer;
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attribute NGD_DRC_MASK of Structure : architecture is 1;
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begin
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-- component instantiation statements
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scuba_vlo_inst : VLO
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port map(Z => scuba_vlo);
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PLLInst_0 : EPLLD1
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-- synopsys translate_off
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generic map(CLKOK_BYPASS => "DISABLED", CLKOS_BYPASS => "DISABLED",
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CLKOP_BYPASS => "DISABLED", PHASE_CNTL => "STATIC", DUTY => 8,
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PHASEADJ => "0.0", CLKOK_DIV => 2, CLKOP_DIV => 4, CLKFB_DIV => 14,
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CLKI_DIV => 5)
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-- synopsys translate_on
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port map(CLKI => CLK, CLKFB => CLKOP_t, RST => scuba_vlo,
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RSTK => scuba_vlo, DPAMODE => scuba_vlo, DRPAI3 => scuba_vlo,
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DRPAI2 => scuba_vlo, DRPAI1 => scuba_vlo, DRPAI0 => scuba_vlo,
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DFPAI3 => scuba_vlo, DFPAI2 => scuba_vlo, DFPAI1 => scuba_vlo,
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DFPAI0 => scuba_vlo, PWD => scuba_vlo, CLKOP => CLKOP_t,
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CLKOS => open, CLKOK => open, LOCK => LOCK, CLKINTFB => open);
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CLKOP <= CLKOP_t;
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end Structure;
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-- synopsys translate_off
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library xp2;
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configuration Structure_CON of pll0 is
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for Structure
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for all : VLO
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use entity xp2.VLO(V);
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end for;
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for all : EPLLD1
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use entity xp2.EPLLD1(V);
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end for;
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end for;
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end Structure_CON;
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-- synopsys translate_on
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