Markus Koch
943febcb99
For low ratios of the two clock domains, the slow clock domain would receive incorrect data as the fast (PHY) clock domain's data output would have already updated with the first bit of the next byte by the time the slow (system) clock domain read it. This fix registers the data in the source clock domain as opposed to the destination clock domain. This is allowed because the valid strobe is synchronized in a way to guarantee that data has been valid for a while when it becomes asserted. Additionally, `phy_out.rx_data` and `phy_out.rx_data_valid` are no longer registered in the destination (system) clock domain as this now introduces unnecessary latency. Also, this was broken the way it was anyway as `rx_active` and `rx_error` would've also had to be registered to keep all timings in sync. |
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| .externalToolBuilders | ||
| .settings | ||
| bench | ||
| cocotb | ||
| demo/lattice_brevia2 | ||
| design | ||
| doc | ||
| trashernet | ||
| .gitignore | ||
| .gitmodules | ||
| .library_mapping.xml | ||
| .project | ||
| README.MD | ||
| run.py | ||
Trashernet
Trashernet is a very trashy Ethernet stack for FPGAs written in VHDL aiming to cover all OSI layers:
- Layer 1, Physical:
trashernet_phy - Layer 2, Data link:
trashernet_mac,trashernet_eth,trashernet_arp - Layer 3, Network:
trashernet_ipv4,trashernet_ipv4prot,trashernet_icmp
When writing it, the following were the main design philosophies:
- Standards are nice and all, but this, it just needs to work.
- Hardware is expensive, LOC are not. So let's do everything we can inside the FPGA.
- If there's a feature that feels optional even though it isn't, it is. See 1. if in doubt.
IMPORTANT: This code (and HW suggestions) violate the Ethernet standard in many ways. Do not use in proper (especially commercial) products.
Hardware
- RX: Use resistors behind Ethernet magnetics to reduce Ethernet RX voltage levels (0 +-2.5V) to LVPECL voltage levels (1.65V +-400mV). Or LVDS if your FPGA can't handle LVPECL. Also, pull up/down resistors help to avoid glitchy behavior with no cable connected or little data activity.
- TX: Meh, a series current limiting resistor is good enough. Drive two outputs differentially to increase the voltage swing. (Technically not true antivalent signals as there's also the "off" state with both disabled.)
Notes:
- The RX pull up/downs are probably not the best idea, and fixable in a better way. But for now, this shall work -- and suffice!
- On the TX side, I'm grossly overloading the drivers. A line driver would probably be a good idea. Or you can just parallel multiple outputs ;D
Stats
Sythesized for a Lattice LFXP2-5E FPGA using LSE / Diamond v3.12:
| Configuration | Slices | LUT4 | Registers |
|---|---|---|---|
trashernet_phy |
115 | 188 | 91 |
License
This Source Code Form is subject to the terms of the Mozilla Public License, v. 2.0.
The Trashernet logo uses graphics from svgrepo.com, which are released under the Creative Commons CC0 license, granting the right to freely adapt and use them in any context. Thank you for making these available:
- Trash can: https://www.svgrepo.com/svg/66604/trash
- Ethernet jack: https://www.svgrepo.com/svg/292518/ethernet
The font used in the logo, "White Rabbit" by Matthew Welch, is also released on a free-to-use basis. Thank you!
- White Rabbit: https://www.fontsquirrel.com/fonts/white-rabbit