243 lines
7.5 KiB
VHDL
243 lines
7.5 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- trashernet_mac.vhd : Ethernet OSI Layer 2, Data Link
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-- Implements packet handling and MAC-Layer en/decoding.
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.trashernet_pkg.all;
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entity trashernet_mac is
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port(
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-- Global
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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-- PHY signals
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rx_data : in byte; -- RX Data
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rx_data_valid : in std_logic; -- RX Data valid
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rx_active : in std_logic; -- RX of packet in progress
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tx_data : out byte; -- TX Data
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tx_data_en : out std_logic; -- Transmitter enable
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tx_data_ack : in std_logic; -- Latched data_tx
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tx_active : in std_logic; -- Transmitter active
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carrier_detect : in std_logic; -- Carrier detected
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rx_error : in std_logic; -- Receive error
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-- MAC signals
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rx_mac_destination : out mac_addr_t; -- Destination MAC address
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rx_mac_source : out mac_addr_t; -- Source MAC address
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rx_mac_ethertype : out ethertype_t; -- Ethertype or length
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rx_mac_data : out byte; -- Ethernet data (after Ethertype)
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rx_mac_valid : out std_logic; -- `rx_mac` values (headers + data) are valid
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rx_mac_header_rcv : out std_logic; -- `rx_mac` header have been received and are valid
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rx_mac_crc_ok : out std_logic; -- End of packet, CRC OK (strobe independent from other rx_mac fields)
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rx_mac_crc_error : out std_logic; -- End of packet, CRC invalid
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tx_mac_destination : in mac_addr_t; -- Destination MAC address
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tx_mac_source : in mac_addr_t; -- Source MAC address
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tx_mac_ethertype : in ethertype_t; -- Ethertype or length
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tx_mac_data : in byte; -- Payload
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tx_mac_data_en : in std_logic; -- Start (and keep) transmitting a frame
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tx_mac_data_ack : out std_logic -- The byte on `tx_mac_data` has been latched. Update to next word.
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);
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end entity trashernet_mac;
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architecture rtl of trashernet_mac is
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constant ETH_POLYNOMIAL : std_logic_vector(31 downto 0) := x"04C11DB7";
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begin
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rx : block
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type state_t is (HEAD, PAYLOAD);
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constant HEAD_LENGTH : integer := rx_mac_destination'length + rx_mac_source'length + rx_mac_ethertype'length;
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constant CRC_LENGTH : integer := 4;
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signal state : state_t;
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signal sr_head : byte_vector(0 to HEAD_LENGTH - 1);
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constant BYTE_COUNT_MAX : integer := maximum(HEAD_LENGTH, CRC_LENGTH) - 1;
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signal byte_count : integer range 0 to BYTE_COUNT_MAX;
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signal sr_payload : byte_vector(0 to 4);
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signal crc : std_logic_vector(ETH_POLYNOMIAL'range);
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signal crc_ok : std_logic;
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signal crc_clear : std_logic;
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begin
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crc_inst : entity work.crc
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generic map(
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POLYNOMIAL => ETH_POLYNOMIAL,
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START => x"FFFFFFFF",
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FINAL_XOR => x"FFFFFFFF",
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REVERSE_OUT => true
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)
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port map(
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clk => clk,
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rst => rst,
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data => rx_data,
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data_valid => rx_data_valid,
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crc_clear => crc_clear,
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crc_out => crc
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);
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crc_ok <= '1' when crc = x"2144DF1C" else '0';
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main : process(clk, rst) is
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begin
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if rst then
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byte_count <= 0;
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rx_mac_valid <= '0';
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rx_mac_crc_error <= '0';
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rx_mac_crc_ok <= '0';
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rx_mac_header_rcv <= '0';
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crc_clear <= '0';
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elsif rising_edge(clk) then
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rx_mac_valid <= '0';
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rx_mac_crc_error <= '0';
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rx_mac_crc_ok <= '0';
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rx_mac_header_rcv <= '0';
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crc_clear <= '0';
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case state is
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when HEAD =>
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if rx_data_valid then
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sr_head <= sr_head(sr_head'low + 1 to sr_head'high) & rx_data;
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if byte_count = (HEAD_LENGTH - 1) then
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state <= PAYLOAD;
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byte_count <= 0;
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rx_mac_header_rcv <= '1';
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end if;
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if (byte_count /= BYTE_COUNT_MAX) then
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byte_count <= byte_count + 1;
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end if;
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end if;
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when PAYLOAD =>
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if rx_data_valid then
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sr_payload <= sr_payload(sr_payload'low + 1 to sr_payload'high) & rx_data;
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if byte_count = CRC_LENGTH then
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rx_mac_valid <= '1';
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else
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byte_count <= byte_count + 1;
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end if;
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end if;
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if not rx_active then
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rx_mac_crc_ok <= crc_ok;
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rx_mac_crc_error <= not crc_ok;
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end if;
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if rx_error then
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rx_mac_crc_error <= '1';
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end if;
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end case;
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if (not rx_active) or rx_error then
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byte_count <= 0;
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state <= HEAD;
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crc_clear <= '1';
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end if;
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end if;
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end process main;
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rx_mac_destination <= sr_head(0 to 5);
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rx_mac_source <= sr_head(6 to 11);
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rx_mac_ethertype <= sr_head(12 to 13);
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rx_mac_data <= sr_payload(0);
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end block rx;
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tx : block
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type tx_state_t is (IDLE, HEADER, DATA, TXCRC);
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signal tx_state : tx_state_t;
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signal sr : byte_vector(0 to tx_mac_destination'length + tx_mac_source'length + tx_mac_ethertype'length - 1);
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constant BIT_CNT_MAX : integer := sr'high;
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signal byte_cnt : integer range 0 to BIT_CNT_MAX;
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signal crc : std_logic_vector(ETH_POLYNOMIAL'range);
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signal crc_clear : std_logic;
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signal crc_valid : std_logic;
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begin
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crc_inst : entity work.crc
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generic map(
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POLYNOMIAL => ETH_POLYNOMIAL,
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START => x"FFFFFFFF",
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FINAL_XOR => x"FFFFFFFF",
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REVERSE_OUT => true
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)
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port map(
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clk => clk,
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rst => rst,
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data => tx_data,
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data_valid => crc_valid,
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crc_clear => crc_clear,
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crc_out => crc
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);
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tx_main : process(clk, rst) is
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begin
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if rst then
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tx_mac_data_ack <= '0';
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elsif rising_edge(clk) then
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tx_mac_data_ack <= '0';
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crc_valid <= '0';
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if tx_data_ack then
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sr <= sr(sr'low + 1 to sr'high) & x"00";
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crc_valid <= '1';
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if byte_cnt /= 0 then
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byte_cnt <= byte_cnt - 1;
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end if;
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end if;
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case tx_state is
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when IDLE =>
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if not tx_active and tx_mac_data_en then
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sr(0 to 7) <= byte_vector'(0 to 6 => x"55", 7 => x"D5");
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byte_cnt <= 7;
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tx_state <= HEADER;
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end if;
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when HEADER =>
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if (tx_data_ack = '1') and (byte_cnt = 0) then -- Sync Header TX complete
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sr <= tx_mac_destination & tx_mac_source & tx_mac_ethertype;
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crc_valid <= '1';
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byte_cnt <= BIT_CNT_MAX;
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tx_state <= DATA;
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end if;
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when DATA =>
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if (tx_data_ack = '1') and (byte_cnt = 0) then -- MAC Header TX complete
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if tx_mac_data_en then
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sr(0) <= tx_mac_data;
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tx_mac_data_ack <= '1';
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else
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sr(0 to 3) <= (crc(7 downto 0), crc(15 downto 8), crc(23 downto 16), crc(31 downto 24));
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byte_cnt <= 4 - 1;
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tx_state <= TXCRC;
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end if;
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end if;
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when TXCRC =>
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if (tx_data_ack = '1') and (byte_cnt = 0) then -- CRC TX complete
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tx_state <= IDLE;
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end if;
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end case;
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end if;
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end process tx_main;
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tx_data_en <= '1' when tx_state /= IDLE else '0';
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crc_clear <= '1' when tx_state = HEADER else '0';
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tx_data <= sr(sr'low);
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end block tx;
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end architecture rtl;
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