27 lines
710 B
VHDL
27 lines
710 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library trashernet;
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use trashernet.trashernet_types.all;
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package bench_pkg is
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procedure send_data(signal rx_p : inout std_logic; constant data : in byte_vector);
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end package bench_pkg;
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package body bench_pkg is
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procedure send_data(signal rx_p : inout std_logic; constant data : in byte_vector) is
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begin
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for i in data'low to data'high loop
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report (" TX Byte: " & to_hstring(data(i)));
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for j in data(i)'low to data(i)'high loop
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rx_p <= not data(i)(j);
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wait for 50 ns;
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rx_p <= data(i)(j);
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wait for 50 ns;
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end loop;
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end loop;
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wait for 16 us; -- IPG
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report "Frame TX complete";
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end procedure send_data;
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end package body bench_pkg;
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