69 lines
2.1 KiB
VHDL
69 lines
2.1 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- crc.vhd : Generic CRC implementation
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity crc is
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generic(
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POLYNOMIAL : std_logic_vector; -- Polynomial, leading '1' is implicit
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START : std_logic_vector; -- CRC start value (after `crc_clear`)
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FINAL_XOR : std_logic_vector; -- CRC will be XORed with this value on `crc_out`
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REVERSE_OUT : boolean -- Bit reverse the output vector
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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data : in std_logic_vector;
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data_valid : in std_logic;
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crc_clear : in std_logic;
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crc_out : out std_logic_vector(POLYNOMIAL'range)
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);
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end entity crc;
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architecture rtl of crc is
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signal crc_i : std_logic_vector(crc_out'range);
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function reverse_bits(slv : std_logic_vector) return std_logic_vector is
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variable r : std_logic_vector(slv'range);
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begin
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for i in slv'low to slv'high loop
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r(i) := slv(r'low + slv'high - i);
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end loop;
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return r;
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end function reverse_bits;
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begin
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crc_calc : process(clk, rst) is
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variable crc_v : std_logic_vector(crc_out'range);
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variable fb : std_logic;
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begin
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if rst then
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crc_i <= START;
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elsif rising_edge(clk) then
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if data_valid then
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crc_v := crc_i;
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for i in data'low to data'high loop
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fb := data(i) xor crc_v(crc_v'high);
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crc_v := (crc_v(crc_v'high - 1 downto crc_v'low) & '0') xor (POLYNOMIAL and fb);
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end loop;
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crc_i <= crc_v;
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end if;
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if crc_clear then
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crc_i <= START;
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end if;
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end if;
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end process crc_calc;
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crc_out <= reverse_bits(crc_i xor FINAL_XOR) when REVERSE_OUT else (crc_i xor FINAL_XOR);
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end architecture rtl;
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