444 lines
12 KiB
VHDL
444 lines
12 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- top_hwitl.vhd: Top level design for hardware-in-the-loop tests
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--
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-- Target: Simulation
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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entity top_hwitl is
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port(
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clk : in std_logic;
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rst_n : in std_logic;
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rx_p : in std_logic;
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tx_p : out std_logic;
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tx_n : out std_logic;
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led_n : out std_logic_vector(7 downto 0); -- @suppress: Used in different architectures
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button_n : in std_logic_vector(3 downto 0); -- @suppress: Used in different architectures
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debug_data : out std_logic_vector(7 downto 0) -- @suppress: Used in different architectures
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);
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end entity top_hwitl;
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architecture mac of top_hwitl is
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component pll0
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port(
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CLK : in std_logic;
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CLKOP : out std_logic;
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LOCK : out std_logic
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);
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end component pll0;
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constant F_CLK : integer := 50000000;
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constant F_CLK_PHY : integer := 140000000;
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constant ETH_CONFIG : configuration_t := (
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mac_address => (x"00", x"ff", x"ff", x"11", x"22", x"33")
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);
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signal rst : std_logic;
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signal clk_phy : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal mac_out : mac_out_t;
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signal mac_in : mac_in_t;
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type status_t is (IDLE, TX);
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signal state : status_t;
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constant BYTE_CNT_MAX : integer := 100;
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signal byte_cnt : integer range 0 to BYTE_CNT_MAX;
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constant TMO_MAX : integer := integer(round((real(F_CLK) * 0.25))) - 1;
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signal tmo : integer range 0 to TMO_MAX;
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begin
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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mac_out => mac_out,
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mac_in => mac_in
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);
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pll0_inst : pll0
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port map(
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CLK => clk,
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CLKOP => clk_phy,
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LOCK => open
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);
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => F_CLK,
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F_CLK_PHY => F_CLK_PHY
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)
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port map(
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clk => clk,
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phy_clk => clk_phy,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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reset_sync : process(clk, rst_n) is
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begin
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if (rst_n = '0') then
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rst <= '1';
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elsif (rising_edge(clk)) then
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rst <= '0';
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end if;
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end process reset_sync;
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receiver : process(clk, rst) is
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begin
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if rst then
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state <= IDLE;
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mac_in.tx_mac_data_en <= '0';
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tmo <= 0;
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elsif rising_edge(clk) then
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if (tmo /= 0) then
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tmo <= tmo - 1;
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end if;
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case state is
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when IDLE =>
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if mac_out.rx_mac_crc_ok then
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if (mac_out.rx_header.mac_destination = ETH_CONFIG.mac_address) then -- Note: We won't respond to broadcasts!
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state <= TX;
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byte_cnt <= BYTE_CNT_MAX;
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mac_in.tx_header.mac_destination <= mac_out.rx_header.mac_source;
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end if;
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end if;
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if tmo = 0 then
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state <= TX;
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byte_cnt <= BYTE_CNT_MAX;
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mac_in.tx_header.mac_destination <= (others => x"FF");
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end if;
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when TX =>
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tmo <= TMO_MAX;
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mac_in.tx_header.mac_ethertype <= (x"00", std_logic_vector(to_unsigned(BYTE_CNT_MAX, 8)));
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mac_in.tx_mac_data_en <= '1';
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mac_in.tx_mac_data <= std_logic_vector(to_unsigned(byte_cnt, 8));
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if mac_out.tx_mac_data_ack then
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if byte_cnt = 1 then
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mac_in.tx_mac_data_en <= '0';
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state <= IDLE;
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else
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byte_cnt <= byte_cnt - 1;
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end if;
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end if;
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end case;
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end if;
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end process receiver;
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mac_in.tx_header.mac_source <= ETH_CONFIG.mac_address;
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debug_data(0) <= tx_p;
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debug_data(1) <= tx_n;
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end architecture mac;
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-- -------------------------------------------------------------------------- --
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-- top_hwitl (eth)
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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architecture eth of top_hwitl is
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component pll0
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port(
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CLK : in std_logic;
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CLKOP : out std_logic;
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LOCK : out std_logic
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);
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end component pll0;
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constant F_CLK : integer := 50000000;
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constant F_CLK_PHY : integer := 140000000;
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constant ETH_CONFIG : configuration_t := (
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mac_address => (x"00", x"FF", x"FF", x"11", x"22", x"33")
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);
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constant IP_CONFIG : ipv4_configuration_t := (
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ip_address => (x"C0", x"A8", x"02", x"02"),
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subnet_mask => (x"FF", x"FF", x"FF", x"00"),
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gateway => (x"C0", x"A8", x"02", x"01")
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);
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signal rst : std_logic;
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signal clk_phy : std_logic;
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signal phy_out : phy_out_t;
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signal phy_in : phy_in_t;
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signal mac_out : mac_out_t;
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signal mac_in : mac_in_t;
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constant PROT_ARP : integer := 0;
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constant PROT_IPV4 : integer := 1;
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constant ETHERNET_II_PROTOCOLS : ethernet_ii_protocol_vector := (
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PROT_ARP => ETHERNET_II_PROTOCOL_ARP,
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PROT_IPV4 => ETHERNET_II_PROTOCOL_IPV4
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);
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signal ethernet_i_out : ethernet_i_out_t;
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signal ethernet_i_in : ethernet_i_in_t;
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signal ethernet_ii_out : ethernet_ii_out_vector(ETHERNET_II_PROTOCOLS'range);
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signal ethernet_ii_in : ethernet_ii_in_vector(ETHERNET_II_PROTOCOLS'range);
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signal arp_out : arp_out_t;
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signal arp_in : arp_in_t;
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signal ipv4_out : ipv4_out_t;
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signal ipv4_in : ipv4_in_t;
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constant IPROT_ICMP : integer := 0;
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constant IPROT_UDP : integer := 1;
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constant IPV4_PROTOCOLS : ipv4_protocol_vector := (
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IPROT_ICMP => IPV4_PROTOCOL_ICMP,
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IPROT_UDP => IPV4_PROTOCOL_UDP
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);
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signal ipv4_protocol_out : ipv4_protocol_out_vector(IPV4_PROTOCOLS'range);
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signal ipv4_protocol_in : ipv4_protocol_in_vector(IPV4_PROTOCOLS'range);
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begin
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trashernet_ipv4prot_inst : entity trashernet.trashernet_ipv4prot
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generic map(
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IPV4_PROTOCOLS => IPV4_PROTOCOLS
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)
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port map(
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clk => clk,
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rst => rst,
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ipv4_out => ipv4_out,
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ipv4_in => ipv4_in,
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ipv4_protocol_out => ipv4_protocol_out,
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ipv4_protocol_in => ipv4_protocol_in
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);
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trashernet_ipv4_inst : entity trashernet.trashernet_ipv4
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port map(
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clk => clk,
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rst => rst,
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ipv4_config => IP_CONFIG,
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arp_out => arp_out,
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arp_in => arp_in,
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ethernet_ii_out => ethernet_ii_out(PROT_IPV4),
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ethernet_ii_in => ethernet_ii_in(PROT_IPV4),
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ipv4_out => ipv4_out,
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ipv4_in => ipv4_in
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);
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trashernet_arp_inst : entity trashernet.trashernet_arp
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generic map(
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SYSTICK_FREQ => F_CLK
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)
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port map(
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clk => clk,
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rst => rst,
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systick => '1',
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mac_config => ETH_CONFIG,
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ip_config => IP_CONFIG,
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arp_out => arp_out,
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arp_in => arp_in,
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ethernet_ii_out => ethernet_ii_out(PROT_ARP),
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ethernet_ii_in => ethernet_ii_in(PROT_ARP)
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);
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ethernet_i_in <= ethernet_i_in_t'(
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tx_mac_address => (others => (others => '-')),
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tx_data => (others => '-'),
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tx_en => '0',
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tx_length => (others => '-')
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);
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trashernet_eth_inst : entity trashernet.trashernet_eth
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generic map(
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ETHERNET_II_PROTOCOLS => ETHERNET_II_PROTOCOLS
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)
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port map(
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clk => clk,
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rst => rst,
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mac_out => mac_out,
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mac_in => mac_in,
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config => ETH_CONFIG,
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ethernet_i_out => ethernet_i_out,
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ethernet_i_in => ethernet_i_in,
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ethernet_ii_out => ethernet_ii_out,
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ethernet_ii_in => ethernet_ii_in
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);
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trashernet_mac_inst : entity trashernet.trashernet_mac
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port map(
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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mac_out => mac_out,
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mac_in => mac_in
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);
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pll0_inst : pll0
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port map(
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CLK => clk,
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CLKOP => clk_phy,
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LOCK => open
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);
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trashernet_phy_cdc_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => F_CLK,
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F_CLK_PHY => F_CLK_PHY
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)
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port map(
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clk => clk,
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phy_clk => clk_phy,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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reset_sync : process(clk, rst_n) is
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begin
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if (rst_n = '0') then
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rst <= '1';
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elsif (rising_edge(clk)) then
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rst <= '0';
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end if;
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end process reset_sync;
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receiver : process(clk, rst) is
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begin
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if rst then
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elsif rising_edge(clk) then
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if ethernet_i_out.rx_header_rcv then
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report "RX ETH-I: " & to_string(to_integer(ethernet_i_out.rx_length));
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end if;
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if (ethernet_ii_out(PROT_ARP).rx_header_rcv) then
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report "RX ARP";
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end if;
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if (ethernet_ii_out(PROT_IPV4).rx_header_rcv) then
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report "RX IP";
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end if;
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if ipv4_out.rx_data_valid then
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report "RX IP data: " & to_hstring(ipv4_out.rx_data);
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end if;
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if ipv4_out.rx_ok_stb then
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report "RX IP OK";
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end if;
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if ipv4_out.rx_error_stb then
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report "RX IP error";
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end if;
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if ipv4_out.rx_header_rcv then
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report "RX IP start. PROT=" & to_hstring(ipv4_out.rx_protocol) & ", FROM=" & ip_to_string(ipv4_out.rx_ip_address);
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end if;
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end if;
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end process receiver;
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udp : process(clk) is
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begin
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if rising_edge(clk) then
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if ipv4_protocol_out(IPROT_UDP).rx_header_rcv then
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report "Receive UDP";
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end if;
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end if;
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end process udp;
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tx_udp_p : block
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type state_t is (IDLE, TX, DONE);
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signal state : state_t;
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constant PACKET : byte_vector := (
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x"10", x"00", -- Source port
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x"04", x"00", -- Destination port
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x"00", x"15", -- Length
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x"00", x"00", -- Checksum (not used)
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x"48", x"65", x"6C", x"6C", x"6F", x"20", x"57", x"6F", x"72", x"6C", x"64", x"21", x"0a" -- Payload
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);
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signal sr : byte_vector(PACKET'range);
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signal cnt : integer range 0 to sr'length - 1;
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begin
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tx_udp : process(clk, rst) is
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begin
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if rst then
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state <= IDLE;
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elsif rising_edge(clk) then
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case state is
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when IDLE =>
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if button_n(0) = '0' then
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state <= TX;
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sr <= PACKET;
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cnt <= sr'length - 1;
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report "UDP: Start TX";
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end if;
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when TX =>
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if ipv4_protocol_out(IPROT_UDP).tx_data_ack then
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sr <= sr(sr'low + 1 to sr'high) & x"00";
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if cnt = 0 then
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state <= DONE;
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else
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cnt <= cnt - 1;
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end if;
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end if;
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if ipv4_protocol_out(IPROT_UDP).tx_err_stb then
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report "UDP: TX ERROR";
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state <= DONE;
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end if;
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if ipv4_protocol_out(IPROT_UDP).tx_ok_stb then
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report "UDP: TX OK stb in TX state -- that shouldn't happen, right?";
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end if;
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when DONE =>
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null;
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end case;
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end if;
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end process tx_udp;
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ipv4_protocol_in(IPROT_UDP).tx_en <= '1' when state = TX else '0';
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ipv4_protocol_in(IPROT_UDP).tx_ip_address <= (x"C0", x"A8", x"02", x"01");
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ipv4_protocol_in(IPROT_UDP).tx_length <= to_unsigned(sr'length, 16);
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ipv4_protocol_in(IPROT_UDP).tx_data <= sr(0);
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end block tx_udp_p;
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icmp : process(clk) is
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begin
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if rising_edge(clk) then
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if ipv4_protocol_out(IPROT_ICMP).rx_header_rcv then
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report "Receive ICMP";
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end if;
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end if;
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end process icmp;
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end architecture eth;
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