65 lines
1.9 KiB
VHDL
65 lines
1.9 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET - A Trashy Ethernet Stack for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- timer.vhd : Simple Timer
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-- Implements a very simple integer timer
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity timer is
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generic(
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F_TICK : integer; -- Frequency of `tick` (or `clk` if tick is tied to '1')
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DURATION : time; -- Duration of the timer
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AUTOSTART : boolean := false -- Automatically start the timer after reset
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);
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port(
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clk : in std_logic; -- Global clock
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rst : in std_logic; -- Asynchronous reset
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tick : in std_logic; -- Timer enable
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start : in std_logic; -- (Re-)start timer
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expired : out std_logic; -- Timer is expired
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expired_stb : out std_logic -- Strobe when timer reaches zero
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);
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end entity timer;
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architecture rtl of timer is
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constant PERIOD : time := 1 sec / real(F_TICK);
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constant TICKS : integer := integer(DURATION / PERIOD);
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signal counter : integer range 0 to TICKS;
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begin
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timer_p : process(clk, rst) is
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begin
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if rst then
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counter <= TICKS when AUTOSTART else 0;
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expired_stb <= '0';
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elsif rising_edge(clk) then
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expired_stb <= '0';
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if tick then
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if counter = 1 then
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expired_stb <= '1';
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end if;
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if counter /= 0 then
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counter <= counter - 1;
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end if;
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end if;
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if start then
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counter <= TICKS;
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end if;
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end if;
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end process timer_p;
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expired <= not start when counter = 0 else '0';
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end architecture rtl;
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