fpga/ws2812b-vhdl
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Added gamma correction to rainbow example

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This commit is contained in:
Markus Koch 2016-10-16 14:25:30 +02:00
parent f7444c25d5
commit 21d75d5d2f
5 changed files with 129 additions and 12 deletions
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56
bench/bench_demo_rainbow.vhd Normal file
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@ -0,0 +1,56 @@
-- ----------------------------------------------------------------------------
-- WS2812B CONTROLLER FOR FPGAS
-- ----------------------------------------------------------------------------
-- bench_demo_rainbow.vhd : Testbench for the rainbow demo.
-- ----------------------------------------------------------------------------
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- Created on : 2016/10/16
-- License : Mozilla Public License (MPL) Version 2
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library design;
use design.all;
entity bench_demo_rainbow is
end entity bench_demo_rainbow;
architecture RTL of bench_demo_rainbow is
signal clk : std_logic;
signal rst_hw : std_logic;
signal btn_n : std_logic;
signal so : std_logic;
begin
demo_rainbow_inst : entity design.demo_rainbow
port map(
clk => clk,
rst_hw => rst_hw,
btn_n => btn_n,
so => so
);
clock_driver : process
constant period : time := 20 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
test_p : process is
begin
rst_hw <= '0';
btn_n <= '1';
wait for 20 ns;
rst_hw <= '1';
wait;
end process test_p;
end architecture RTL;

31
design/demo_rainbow.vhd
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@ -48,6 +48,9 @@ architecture RTL of demo_rainbow is
signal pixData_red : unsigned(7 downto 0); signal pixData_red : unsigned(7 downto 0);
signal pixData_green : unsigned(7 downto 0); signal pixData_green : unsigned(7 downto 0);
signal pixData_blue : unsigned(7 downto 0); signal pixData_blue : unsigned(7 downto 0);
signal pixData_red_corr : std_logic_vector(7 downto 0);
signal pixData_green_corr : std_logic_vector(7 downto 0);
signal pixData_blue_corr : std_logic_vector(7 downto 0);
signal pixData_red_start : unsigned(7 downto 0); signal pixData_red_start : unsigned(7 downto 0);
signal pixData_green_start : unsigned(7 downto 0); signal pixData_green_start : unsigned(7 downto 0);
signal pixData_blue_start : unsigned(7 downto 0); signal pixData_blue_start : unsigned(7 downto 0);
@ -65,6 +68,7 @@ architecture RTL of demo_rainbow is
begin begin
rst <= not rst_hw; rst <= not rst_hw;
-- WS2812B PHY
ws2812b_phy_inst : entity work.ws2812b_phy ws2812b_phy_inst : entity work.ws2812b_phy
generic map( generic map(
f_clk => F_CLK f_clk => F_CLK
@ -73,13 +77,33 @@ begin
clk => clk, clk => clk,
rst => rst, rst => rst,
so => so, so => so,
pixData_red => std_logic_vector(pixData_red), pixData_red => pixData_red_corr,
pixData_green => std_logic_vector(pixData_green), pixData_green => pixData_green_corr,
pixData_blue => std_logic_vector(pixData_blue), pixData_blue => pixData_blue_corr,
pixData_valid => pixData_valid, pixData_valid => pixData_valid,
pixData_next => pixData_next pixData_next => pixData_next
); );
-- Gamma correction
ws2812b_gamma_red_inst : entity work.ws2812b_gamma
port map(
pixelData_in => std_logic_vector(pixData_red),
pixelData_out => pixData_red_corr
);
ws2812b_gamma_green_inst : entity work.ws2812b_gamma
port map(
pixelData_in => std_logic_vector(pixData_green),
pixelData_out => pixData_green_corr
);
ws2812b_gamma_blue_inst : entity work.ws2812b_gamma
port map(
pixelData_in => std_logic_vector(pixData_blue),
pixelData_out => pixData_blue_corr
);
-- Timebase to advance the animation
systick_p : process(clk, rst) is systick_p : process(clk, rst) is
constant cmax : integer := (F_CLK / F_SYSTICK); constant cmax : integer := (F_CLK / F_SYSTICK);
variable cnt : integer range 0 to cmax; variable cnt : integer range 0 to cmax;
@ -98,6 +122,7 @@ begin
end if; end if;
end process systick_p; end process systick_p;
-- Animation generator and renderer
rainbow_p : process(clk, rst) is rainbow_p : process(clk, rst) is
procedure incr(signal col : inout unsigned(7 downto 0); next_transition : in color_transition_t; is_live : boolean) is procedure incr(signal col : inout unsigned(7 downto 0); next_transition : in color_transition_t; is_live : boolean) is
begin begin

15
design/ws2812b_gamma.vhd
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@ -2,7 +2,7 @@
-- WS2812B CONTROLLER FOR FPGAS -- WS2812B CONTROLLER FOR FPGAS
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- ws2812b_gamma.vhd : Gamma correction RAM for the WS2812B LEDs. -- ws2812b_gamma.vhd : Gamma correction RAM for the WS2812B LEDs.
-- : Not yet implemented. -- : Do note that this generates a (fairly large, async) LUT.
-- ---------------------------------------------------------------------------- -- ----------------------------------------------------------------------------
-- Author : Markus Koch <markus@notsyncing.net> -- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None -- Contributors : None
@ -16,14 +16,14 @@ use ieee.numeric_std.all;
entity ws2812b_gamma is entity ws2812b_gamma is
port( port(
clk : in std_logic; pixelData_in : in std_logic_vector(7 downto 0);
rst : in std_logic pixelData_out : out std_logic_vector(7 downto 0)
); );
end entity ws2812b_gamma; end entity ws2812b_gamma;
architecture RTL of ws2812b_gamma is architecture RTL of ws2812b_gamma is
type gamma_table_t is array (0 to 255) of std_logic_vector(7 downto 0); type gamma_table_t is array (0 to 255) of std_logic_vector(7 downto 0);
constant gamme_table : gamma_table_t := ( constant gamma_table : gamma_table_t := (
0 => std_logic_vector(to_unsigned(0, 8)), 0 => std_logic_vector(to_unsigned(0, 8)),
1 => std_logic_vector(to_unsigned(0, 8)), 1 => std_logic_vector(to_unsigned(0, 8)),
2 => std_logic_vector(to_unsigned(0, 8)), 2 => std_logic_vector(to_unsigned(0, 8)),
@ -280,6 +280,7 @@ architecture RTL of ws2812b_gamma is
253 => std_logic_vector(to_unsigned(250, 8)), 253 => std_logic_vector(to_unsigned(250, 8)),
254 => std_logic_vector(to_unsigned(252, 8)), 254 => std_logic_vector(to_unsigned(252, 8)),
255 => std_logic_vector(to_unsigned(255, 8)) 255 => std_logic_vector(to_unsigned(255, 8))
); );
begin begin
end architecture RTL; pixelData_out <= gamma_table(to_integer(unsigned(pixelData_in)));
end architecture RTL;

2
design/ws2812b_phy.vhd
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@ -21,7 +21,7 @@ entity ws2812b_phy is
T1H : real := 0.0000009; T1H : real := 0.0000009;
T0L : real := 0.0000009; T0L : real := 0.0000009;
T1L : real := 0.00000035; T1L : real := 0.00000035;
DEL : real := 0.0000000; -- 0.0000001 DEL : real := 0.0000001; -- 0.0000001
RES : real := 0.00005000 -- Must be bigger than others RES : real := 0.00005000 -- Must be bigger than others
); );
port( port(

35
gtkwave/bench_demo_rainbow.gtkw Normal file
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@ -0,0 +1,35 @@
[*]
[*] GTKWave Analyzer v3.3.76 (w)1999-2016 BSI
[*] Sun Oct 16 10:39:02 2016
[*]
[dumpfile] "/tmp/SigasiCompileCache1957728051622960465/ws2812b/mentor/bench_demo_rainbow.ghw"
[dumpfile_mtime] "Sun Oct 16 10:38:54 2016"
[dumpfile_size] 74301336
[savefile] "/home/markus/projects/sigasiStudio/ws2812b/gtkwave/bench_demo_rainbow.gtkw"
[timestart] 7400000000000
[size] 1920 1023
[pos] -1 -1
*-36.518665 7757800000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_demo_rainbow.
[treeopen] top.bench_demo_rainbow.demo_rainbow_inst.
[sst_width] 205
[signals_width] 183
[sst_expanded] 1
[sst_vpaned_height] 293
@22
#{top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[7:0]} top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[7] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[6] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[5] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[4] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[3] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[2] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[1] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_red[0]
#{top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[7:0]} top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[7] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[6] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[5] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[4] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[3] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[2] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[1] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_green[0]
#{top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[7:0]} top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[7] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[6] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[5] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[4] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[3] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[2] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[1] top.bench_demo_rainbow.demo_rainbow_inst.pixdata_blue[0]
@28
top.bench_demo_rainbow.demo_rainbow_inst.pixcount
top.bench_demo_rainbow.demo_rainbow_inst.color_transition
top.bench_demo_rainbow.demo_rainbow_inst.pixdata_next
top.bench_demo_rainbow.demo_rainbow_inst.pixdata_valid
top.bench_demo_rainbow.demo_rainbow_inst.rst
top.bench_demo_rainbow.demo_rainbow_inst.so
top.bench_demo_rainbow.demo_rainbow_inst.btn_n
top.bench_demo_rainbow.demo_rainbow_inst.rst_hw
top.bench_demo_rainbow.demo_rainbow_inst.clk
[pattern_trace] 1
[pattern_trace] 0