mirror of
https://github.com/cclassic/ws2812b-vhdl
synced 2024-11-24 09:15:05 +01:00
129 lines
3.7 KiB
VHDL
129 lines
3.7 KiB
VHDL
-- ----------------------------------------------------------------------------
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-- WS2812B CONTROLLER FOR FPGAS
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-- ----------------------------------------------------------------------------
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-- top.vhd : Top level design to test the WS2812B controller modules.
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-- : Real demo applications coming soon.
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-- ----------------------------------------------------------------------------
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- Created on : 2016/10/16
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-- License : Mozilla Public License (MPL) Version 2
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-- ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity top is
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port(
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clk : in std_logic;
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rst_hw : in std_logic;
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btn_n : in std_logic;
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so : out std_logic
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);
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end entity top;
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architecture RTL of top is
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constant length : integer := 120;
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signal rst : std_logic;
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signal addr : std_logic_vector(integer(ceil(log2(real(length - 1)))) downto 0);
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signal data_red : std_logic_vector(7 downto 0);
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signal data_green : std_logic_vector(7 downto 0);
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signal data_blue : std_logic_vector(7 downto 0);
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signal dataOut_red : std_logic_vector(7 downto 0);
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signal dataOut_green : std_logic_vector(7 downto 0);
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signal dataOut_blue : std_logic_vector(7 downto 0);
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signal we : std_logic;
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signal render : std_logic;
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signal vsync : std_logic;
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signal done : std_logic;
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signal foo : std_logic_vector(1 downto 0);
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begin
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rst <= not rst_hw;
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foo <= addr(1 downto 0);
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ws2812b_controller_inst : entity work.ws2812b_controller
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generic map(
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length => length,
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f_clk => 50000000
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)
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port map(
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clk => clk,
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rst => rst,
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so => so,
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addr => addr,
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data_red => data_red,
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data_green => data_green,
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data_blue => data_blue,
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dataOut_red => dataOut_red,
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dataOut_green => dataOut_green,
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dataOut_blue => dataOut_blue,
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we => we,
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render => render,
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vsync => vsync
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);
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prog : process(clk, rst) is
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variable colRot : unsigned(1 downto 0);
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variable c2 : integer range 0 to 25000000;
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begin
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if rst = '1' then
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addr <= (others => '1');
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data_red <= (others => '0');
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data_green <= (others => '0');
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data_blue <= (others => '0');
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we <= '0';
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done <= '1';
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c2 := 0;
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colRot := "00";
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render <= '0';
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elsif rising_edge(clk) then
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we <= '0';
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render <= '0';
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if done = '0' then
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addr <= std_logic_vector(unsigned(addr) + 1);
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if to_integer(unsigned(addr)) = length - 1 then
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done <= '1';
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render <= '1';
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end if;
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if unsigned(foo) = colRot then
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data_red <= (others => '1');
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data_green <= (others => '0');
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data_blue <= (others => '0');
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elsif unsigned(foo) = colRot + 1 then
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data_red <= (others => '0');
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data_green <= (others => '1');
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data_blue <= (others => '0');
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elsif unsigned(foo) = colRot + 2 then
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data_red <= (others => '0');
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data_green <= (others => '0');
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data_blue <= (others => '1');
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else
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data_red <= std_logic_vector(to_unsigned(127, 8));
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data_green <= std_logic_vector(to_unsigned(127, 8));
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data_blue <= (others => '0');
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end if;
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if (btn_n = '0') then
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data_red <= (others => '1');
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data_green <= (others => '1');
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data_blue <= (others => '1');
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end if;
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we <= '1';
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else
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if c2 = 10000000 then
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done <= '0';
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c2 := 0;
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colRot := colRot + 1;
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else
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c2 := c2 + 1;
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end if;
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end if;
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end if;
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end process prog;
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end architecture RTL;
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