mirror of
https://github.com/cclassic/ws2812b-vhdl
synced 2024-11-24 09:15:05 +01:00
57 lines
1.4 KiB
VHDL
57 lines
1.4 KiB
VHDL
-- ----------------------------------------------------------------------------
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-- WS2812B CONTROLLER FOR FPGAS
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-- ----------------------------------------------------------------------------
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-- bench_demo_rainbow.vhd : Testbench for the rainbow demo.
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-- ----------------------------------------------------------------------------
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- Created on : 2016/10/16
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-- License : Mozilla Public License (MPL) Version 2
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-- ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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entity bench_demo_rainbow is
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end entity bench_demo_rainbow;
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architecture RTL of bench_demo_rainbow is
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signal clk : std_logic;
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signal rst_hw : std_logic;
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signal btn_n : std_logic;
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signal so : std_logic;
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begin
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demo_rainbow_inst : entity design.demo_rainbow
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port map(
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clk => clk,
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rst_hw => rst_hw,
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btn_n => btn_n,
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so => so
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);
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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test_p : process is
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begin
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rst_hw <= '0';
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btn_n <= '1';
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wait for 20 ns;
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rst_hw <= '1';
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wait;
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end process test_p;
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end architecture RTL;
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