mirror of
https://github.com/cclassic/ws2812b-vhdl
synced 2024-09-29 03:35:06 +02:00
84 lines
2.3 KiB
VHDL
84 lines
2.3 KiB
VHDL
-- ----------------------------------------------------------------------------
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-- WS2812B CONTROLLER FOR FPGAS
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-- ----------------------------------------------------------------------------
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-- bench_ws2812b_phy.vhd : Development testbench for the WS2812B phy module.
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-- ----------------------------------------------------------------------------
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- Created on : 2016/10/16
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-- License : Mozilla Public License (MPL) Version 2
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-- ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ws2812b;
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use ws2812b.all;
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entity bench_ws2812b_phy is
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end entity bench_ws2812b_phy;
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architecture RTL of bench_ws2812b_phy is
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signal clk : std_logic;
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signal rst : std_logic;
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signal so : std_logic;
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signal pixData_red : std_logic_vector(7 downto 0);
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signal pixData_green : std_logic_vector(7 downto 0);
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signal pixData_blue : std_logic_vector(7 downto 0);
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signal pixData_valid : std_logic;
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signal pixData_next : std_logic;
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begin
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clock_driver : process
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constant period : time := 10 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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ws2812b_phy_inst : entity ws2812b.ws2812b_phy
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generic map(
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f_clk => 100000000
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)
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port map(
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clk => clk,
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rst => rst,
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so => so,
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pixData_red => pixData_red,
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pixData_green => pixData_green,
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pixData_blue => pixData_blue,
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pixData_valid => pixData_valid,
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pixData_next => pixData_next
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);
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test : process is
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begin
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pixData_red <= x"00";
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pixData_green <= x"80";
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pixData_blue <= x"01";
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pixData_valid <= '0';
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rst <= '1';
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wait for 20 ns;
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rst <= '0';
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wait for 20 ns;
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pixData_valid <= '1';
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wait until pixData_next = '1'; -- Pix 0
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wait until pixData_next = '1'; -- Pix 1
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pixData_valid <= '0';
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wait until pixData_next = '1'; -- Reset ack
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pixData_valid <= '1';
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wait until pixData_next = '1'; -- Pix 0
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wait until pixData_next = '1'; -- Pix 1
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pixData_valid <= '0';
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wait until pixData_next = '1'; -- Reset ack
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wait;
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end process test;
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end architecture RTL;
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