Update Tiny RISCV SoC for RFU
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# Basic Concept
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# SERV
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Build a "servant". Maybe from fusesoc if I can figure out how, or just manually from source. Should be easy. Has everything I need to get started, so I might not even have to worry about getting my VHDL into the Verilog top level.
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@ -6,16 +6,20 @@ Then run zephyr OS on it. ttps://github.com/olofk/serv has the instructions on t
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ZephyrOS seems to also include some RSA implementations, so that's useful.
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# Commands
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## Commands
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* Build SERVANT for CMOD A7: `fusesoc run --tool=vivado --target=cmod_a7_35t servant`
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* For faster RISCV-IM add multiply divide from `fusesoc library add mdu https://github.com/zeeshanrafique23/mdu`
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# Links
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## Links
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* https://github.com/olofk/serv
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* https://fusesoc.readthedocs.io/en/stable/user/overview.html
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# Interesting Reads
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## Interesting Reads
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* https://riscv.org/blog/2022/07/risc-v-compressed-instructions-for-serv-abdul-wadood-lfx-mentorship-at-risc-v-international/
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* https://riscv.org/blog/2022/07/risc-v-compressed-instructions-for-serv-abdul-wadood-lfx-mentorship-at-risc-v-international/
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# PicoRV32
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Might be an interesting alternative.
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