fpgna/fpgna.kicad_pcb

(kicad_pcb (version 4) (host pcbnew "(2016-02-12 BZR 6554)-stable")

  (general
    (links 156)
    (no_connects 78)
    (area 25.871999 29.997 123.114841 102.157)
    (thickness 1.6)
    (drawings 0)
    (tracks 485)
    (zones 0)
    (modules 8)
    (nets 192)
  )

  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )

  (setup
    (last_trace_width 0.153)
    (trace_clearance 0.153)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.153)
    (segment_width 0.2)
    (edge_width 0.1)
    (via_size 0.5)
    (via_drill 0.3)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.5 1.5)
    (pad_drill 0.6)
    (pad_to_mask_clearance 0)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_ffffffff)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )

  (net 0 "")
  (net 1 /FSMC/DA13)
  (net 2 /FSMC/E1_N)
  (net 3 "Net-(C4-Pad1)")
  (net 4 VFPGA33)
  (net 5 GNDD)
  (net 6 +1V2)
  (net 7 "Net-(R2-Pad2)")
  (net 8 "Net-(R3-Pad2)")
  (net 9 "Net-(P3-Pad3)")
  (net 10 "Net-(P3-Pad5)")
  (net 11 "Net-(P3-Pad1)")
  (net 12 "Net-(P3-Pad7)")
  (net 13 /FSMC/A23)
  (net 14 /FSMC/A19)
  (net 15 /FSMC/A20)
  (net 16 /FSMC/A21)
  (net 17 /FSMC/A22)
  (net 18 "Net-(U4-Pad7)")
  (net 19 "Net-(U4-Pad8)")
  (net 20 "Net-(U4-Pad9)")
  (net 21 "Net-(U4-Pad14)")
  (net 22 "Net-(U4-Pad15)")
  (net 23 "Net-(U4-Pad16)")
  (net 24 "Net-(U4-Pad17)")
  (net 25 "Net-(U4-Pad18)")
  (net 26 "Net-(U4-Pad23)")
  (net 27 "Net-(U4-Pad24)")
  (net 28 "Net-(U4-Pad25)")
  (net 29 "Net-(U4-Pad26)")
  (net 30 "Net-(U4-Pad29)")
  (net 31 "Net-(U4-Pad30)")
  (net 32 "Net-(U4-Pad31)")
  (net 33 "Net-(U4-Pad32)")
  (net 34 "Net-(U4-Pad33)")
  (net 35 "Net-(U4-Pad34)")
  (net 36 "Net-(U4-Pad35)")
  (net 37 "Net-(U4-Pad36)")
  (net 38 /FSMC/BOOT1)
  (net 39 /FSMC/DA4)
  (net 40 /FSMC/DA5)
  (net 41 /FSMC/DA6)
  (net 42 /FSMC/DA7)
  (net 43 /FSMC/DA8)
  (net 44 /FSMC/DA9)
  (net 45 /FSMC/DA10)
  (net 46 /FSMC/DA11)
  (net 47 /FSMC/DA12)
  (net 48 "Net-(U4-Pad47)")
  (net 49 "Net-(U4-Pad48)")
  (net 50 "Net-(U4-Pad51)")
  (net 51 "Net-(U4-Pad52)")
  (net 52 "Net-(U4-Pad53)")
  (net 53 "Net-(U4-Pad54)")
  (net 54 /FSMC/DA14)
  (net 55 /FSMC/DA15)
  (net 56 /FSMC/A16)
  (net 57 /FSMC/A17)
  (net 58 /FSMC/A18)
  (net 59 /FSMC/DA0)
  (net 60 /FSMC/DA1)
  (net 61 "Net-(U4-Pad63)")
  (net 62 "Net-(U4-Pad64)")
  (net 63 "Net-(U4-Pad65)")
  (net 64 "Net-(U4-Pad66)")
  (net 65 "Net-(U4-Pad67)")
  (net 66 "Net-(U4-Pad68)")
  (net 67 "Net-(U4-Pad69)")
  (net 68 "Net-(U4-Pad70)")
  (net 69 "Net-(U4-Pad71)")
  (net 70 "Net-(U4-Pad72)")
  (net 71 "Net-(U4-Pad76)")
  (net 72 "Net-(U4-Pad77)")
  (net 73 "Net-(U4-Pad78)")
  (net 74 "Net-(U4-Pad79)")
  (net 75 "Net-(U4-Pad80)")
  (net 76 /FSMC/DA2)
  (net 77 /FSMC/DA3)
  (net 78 "Net-(U4-Pad83)")
  (net 79 /FSMC/CLK)
  (net 80 /FSMC/OE_N)
  (net 81 /FSMC/WE_N)
  (net 82 /FSMC/WAIT_N)
  (net 83 /FSMC/JTDO)
  (net 84 /FSMC/JRST_N)
  (net 85 "Net-(U4-Pad91)")
  (net 86 "Net-(U4-Pad92)")
  (net 87 /FSMC/ADV_N)
  (net 88 "Net-(U4-Pad94)")
  (net 89 "Net-(U4-Pad95)")
  (net 90 "Net-(U4-Pad96)")
  (net 91 /FSMC/BL0_N)
  (net 92 /FSMC/BL1_N)
  (net 93 VSTM33)
  (net 94 GND)
  (net 95 /powersupply/VCAP1)
  (net 96 /powersupply/VCAP2)
  (net 97 "Net-(C40-Pad1)")
  (net 98 "Net-(C41-Pad1)")
  (net 99 "Net-(U6-Pad5)")
  (net 100 "Net-(U6-Pad31)")
  (net 101 "Net-(U6-Pad35)")
  (net 102 "Net-(R14-Pad1)")
  (net 103 "Net-(U6-Pad38)")
  (net 104 "Net-(U6-Pad39)")
  (net 105 "Net-(U6-Pad40)")
  (net 106 /display/DB0)
  (net 107 /display/DB1)
  (net 108 /display/DB2)
  (net 109 /display/RS)
  (net 110 /display/DB3)
  (net 111 /display/WR)
  (net 112 /display/DB4)
  (net 113 /display/RD)
  (net 114 /display/DB5)
  (net 115 /display/DB8)
  (net 116 /display/DB6)
  (net 117 /display/DB9)
  (net 118 /display/DB7)
  (net 119 /display/DB10)
  (net 120 /display/DB11)
  (net 121 /display/DB12)
  (net 122 /display/DB13)
  (net 123 /display/DB14)
  (net 124 /display/DB15)
  (net 125 /display/CS)
  (net 126 /display/RST)
  (net 127 "Net-(U3-Pad73)")
  (net 128 /display/T_CLK)
  (net 129 /display/T_CS)
  (net 130 /display/T_DIN)
  (net 131 /display/T_BUSY)
  (net 132 /display/T_DOUT)
  (net 133 /display/T_IRQ)
  (net 134 /display/SD_SO)
  (net 135 /display/SD_SCK)
  (net 136 /display/SD_SI)
  (net 137 /display/SD_NSS)
  (net 138 /sdram/DQ0)
  (net 139 /sdram/DQ1)
  (net 140 /sdram/DQ2)
  (net 141 /sdram/DQ3)
  (net 142 /sdram/DQ4)
  (net 143 /sdram/DQ5)
  (net 144 /sdram/DQ6)
  (net 145 /sdram/DQ7)
  (net 146 /sdram/DQML)
  (net 147 /sdram/WE)
  (net 148 /sdram/CAS)
  (net 149 /sdram/RAS)
  (net 150 /sdram/CS)
  (net 151 /sdram/BA0)
  (net 152 /sdram/BA1)
  (net 153 /sdram/A10)
  (net 154 /sdram/A0)
  (net 155 /sdram/A1)
  (net 156 /sdram/A2)
  (net 157 /sdram/A3)
  (net 158 /sdram/A4)
  (net 159 /sdram/A5)
  (net 160 /sdram/A6)
  (net 161 /sdram/A7)
  (net 162 /sdram/A8)
  (net 163 /sdram/A9)
  (net 164 /sdram/A11)
  (net 165 "Net-(U7-Pad36)")
  (net 166 /sdram/CKE)
  (net 167 /sdram/CLK)
  (net 168 /sdram/DQMH)
  (net 169 "Net-(U7-Pad40)")
  (net 170 /sdram/DQ8)
  (net 171 /sdram/DQ9)
  (net 172 /sdram/DQ10)
  (net 173 /sdram/DQ11)
  (net 174 /sdram/DQ12)
  (net 175 /sdram/DQ13)
  (net 176 /sdram/DQ14)
  (net 177 /sdram/DQ15)
  (net 178 "Net-(U3-Pad1)")
  (net 179 "Net-(U3-Pad2)")
  (net 180 "Net-(U3-Pad5)")
  (net 181 "Net-(U3-Pad6)")
  (net 182 "Net-(U3-Pad7)")
  (net 183 "Net-(U3-Pad8)")
  (net 184 "Net-(U3-Pad9)")
  (net 185 "Net-(U3-Pad10)")
  (net 186 "Net-(U3-Pad11)")
  (net 187 "Net-(U3-Pad13)")
  (net 188 "Net-(U3-Pad15)")
  (net 189 "Net-(U3-Pad16)")
  (net 190 "Net-(U3-Pad17)")
  (net 191 "Net-(U3-Pad18)")

  (net_class Default "This is the default net class."
    (clearance 0.153)
    (trace_width 0.153)
    (via_dia 0.5)
    (via_drill 0.3)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net +1V2)
    (add_net /FSMC/A16)
    (add_net /FSMC/A17)
    (add_net /FSMC/A18)
    (add_net /FSMC/A19)
    (add_net /FSMC/A20)
    (add_net /FSMC/A21)
    (add_net /FSMC/A22)
    (add_net /FSMC/A23)
    (add_net /FSMC/ADV_N)
    (add_net /FSMC/BL0_N)
    (add_net /FSMC/BL1_N)
    (add_net /FSMC/BOOT1)
    (add_net /FSMC/CLK)
    (add_net /FSMC/DA0)
    (add_net /FSMC/DA1)
    (add_net /FSMC/DA10)
    (add_net /FSMC/DA11)
    (add_net /FSMC/DA12)
    (add_net /FSMC/DA13)
    (add_net /FSMC/DA14)
    (add_net /FSMC/DA15)
    (add_net /FSMC/DA2)
    (add_net /FSMC/DA3)
    (add_net /FSMC/DA4)
    (add_net /FSMC/DA5)
    (add_net /FSMC/DA6)
    (add_net /FSMC/DA7)
    (add_net /FSMC/DA8)
    (add_net /FSMC/DA9)
    (add_net /FSMC/E1_N)
    (add_net /FSMC/JRST_N)
    (add_net /FSMC/JTDO)
    (add_net /FSMC/OE_N)
    (add_net /FSMC/WAIT_N)
    (add_net /FSMC/WE_N)
    (add_net /display/CS)
    (add_net /display/DB0)
    (add_net /display/DB1)
    (add_net /display/DB10)
    (add_net /display/DB11)
    (add_net /display/DB12)
    (add_net /display/DB13)
    (add_net /display/DB14)
    (add_net /display/DB15)
    (add_net /display/DB2)
    (add_net /display/DB3)
    (add_net /display/DB4)
    (add_net /display/DB5)
    (add_net /display/DB6)
    (add_net /display/DB7)
    (add_net /display/DB8)
    (add_net /display/DB9)
    (add_net /display/RD)
    (add_net /display/RS)
    (add_net /display/RST)
    (add_net /display/SD_NSS)
    (add_net /display/SD_SCK)
    (add_net /display/SD_SI)
    (add_net /display/SD_SO)
    (add_net /display/T_BUSY)
    (add_net /display/T_CLK)
    (add_net /display/T_CS)
    (add_net /display/T_DIN)
    (add_net /display/T_DOUT)
    (add_net /display/T_IRQ)
    (add_net /display/WR)
    (add_net /powersupply/VCAP1)
    (add_net /powersupply/VCAP2)
    (add_net /sdram/A0)
    (add_net /sdram/A1)
    (add_net /sdram/A10)
    (add_net /sdram/A11)
    (add_net /sdram/A2)
    (add_net /sdram/A3)
    (add_net /sdram/A4)
    (add_net /sdram/A5)
    (add_net /sdram/A6)
    (add_net /sdram/A7)
    (add_net /sdram/A8)
    (add_net /sdram/A9)
    (add_net /sdram/BA0)
    (add_net /sdram/BA1)
    (add_net /sdram/CAS)
    (add_net /sdram/CKE)
    (add_net /sdram/CLK)
    (add_net /sdram/CS)
    (add_net /sdram/DQ0)
    (add_net /sdram/DQ1)
    (add_net /sdram/DQ10)
    (add_net /sdram/DQ11)
    (add_net /sdram/DQ12)
    (add_net /sdram/DQ13)
    (add_net /sdram/DQ14)
    (add_net /sdram/DQ15)
    (add_net /sdram/DQ2)
    (add_net /sdram/DQ3)
    (add_net /sdram/DQ4)
    (add_net /sdram/DQ5)
    (add_net /sdram/DQ6)
    (add_net /sdram/DQ7)
    (add_net /sdram/DQ8)
    (add_net /sdram/DQ9)
    (add_net /sdram/DQMH)
    (add_net /sdram/DQML)
    (add_net /sdram/RAS)
    (add_net /sdram/WE)
    (add_net GND)
    (add_net GNDD)
    (add_net "Net-(C4-Pad1)")
    (add_net "Net-(C40-Pad1)")
    (add_net "Net-(C41-Pad1)")
    (add_net "Net-(P3-Pad1)")
    (add_net "Net-(P3-Pad3)")
    (add_net "Net-(P3-Pad5)")
    (add_net "Net-(P3-Pad7)")
    (add_net "Net-(R14-Pad1)")
    (add_net "Net-(R2-Pad2)")
    (add_net "Net-(R3-Pad2)")
    (add_net "Net-(U3-Pad1)")
    (add_net "Net-(U3-Pad10)")
    (add_net "Net-(U3-Pad11)")
    (add_net "Net-(U3-Pad13)")
    (add_net "Net-(U3-Pad15)")
    (add_net "Net-(U3-Pad16)")
    (add_net "Net-(U3-Pad17)")
    (add_net "Net-(U3-Pad18)")
    (add_net "Net-(U3-Pad2)")
    (add_net "Net-(U3-Pad5)")
    (add_net "Net-(U3-Pad6)")
    (add_net "Net-(U3-Pad7)")
    (add_net "Net-(U3-Pad73)")
    (add_net "Net-(U3-Pad8)")
    (add_net "Net-(U3-Pad9)")
    (add_net "Net-(U4-Pad14)")
    (add_net "Net-(U4-Pad15)")
    (add_net "Net-(U4-Pad16)")
    (add_net "Net-(U4-Pad17)")
    (add_net "Net-(U4-Pad18)")
    (add_net "Net-(U4-Pad23)")
    (add_net "Net-(U4-Pad24)")
    (add_net "Net-(U4-Pad25)")
    (add_net "Net-(U4-Pad26)")
    (add_net "Net-(U4-Pad29)")
    (add_net "Net-(U4-Pad30)")
    (add_net "Net-(U4-Pad31)")
    (add_net "Net-(U4-Pad32)")
    (add_net "Net-(U4-Pad33)")
    (add_net "Net-(U4-Pad34)")
    (add_net "Net-(U4-Pad35)")
    (add_net "Net-(U4-Pad36)")
    (add_net "Net-(U4-Pad47)")
    (add_net "Net-(U4-Pad48)")
    (add_net "Net-(U4-Pad51)")
    (add_net "Net-(U4-Pad52)")
    (add_net "Net-(U4-Pad53)")
    (add_net "Net-(U4-Pad54)")
    (add_net "Net-(U4-Pad63)")
    (add_net "Net-(U4-Pad64)")
    (add_net "Net-(U4-Pad65)")
    (add_net "Net-(U4-Pad66)")
    (add_net "Net-(U4-Pad67)")
    (add_net "Net-(U4-Pad68)")
    (add_net "Net-(U4-Pad69)")
    (add_net "Net-(U4-Pad7)")
    (add_net "Net-(U4-Pad70)")
    (add_net "Net-(U4-Pad71)")
    (add_net "Net-(U4-Pad72)")
    (add_net "Net-(U4-Pad76)")
    (add_net "Net-(U4-Pad77)")
    (add_net "Net-(U4-Pad78)")
    (add_net "Net-(U4-Pad79)")
    (add_net "Net-(U4-Pad8)")
    (add_net "Net-(U4-Pad80)")
    (add_net "Net-(U4-Pad83)")
    (add_net "Net-(U4-Pad9)")
    (add_net "Net-(U4-Pad91)")
    (add_net "Net-(U4-Pad92)")
    (add_net "Net-(U4-Pad94)")
    (add_net "Net-(U4-Pad95)")
    (add_net "Net-(U4-Pad96)")
    (add_net "Net-(U6-Pad31)")
    (add_net "Net-(U6-Pad35)")
    (add_net "Net-(U6-Pad38)")
    (add_net "Net-(U6-Pad39)")
    (add_net "Net-(U6-Pad40)")
    (add_net "Net-(U6-Pad5)")
    (add_net "Net-(U7-Pad36)")
    (add_net "Net-(U7-Pad40)")
    (add_net VFPGA33)
    (add_net VSTM33)
  )

  (module smd:TSOP-54 (layer F.Cu) (tedit 56C6D015) (tstamp 56C6E984)
    (at 66.8 42.9)
    (path /563244F7/56C702B2)
    (fp_text reference U7 (at -1.9 -6.5 90) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value IS42S16800F (at 10.05 -5.8) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_circle (center 0.323502 -2) (end 0.55 -1.6) (layer F.SilkS) (width 0.15))
    (fp_line (start 21.5 -11.05) (end -0.7 -11.05) (layer F.SilkS) (width 0.15))
    (fp_line (start 21.5 -0.95) (end 21.5 -11.05) (layer F.SilkS) (width 0.15))
    (fp_line (start -0.7 -0.95) (end 21.5 -0.95) (layer F.SilkS) (width 0.15))
    (fp_line (start -0.7 -11.05) (end -0.7 -0.95) (layer F.SilkS) (width 0.15))
    (pad 1 smd rect (at 0 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 2 smd rect (at 0.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 138 /sdram/DQ0))
    (pad 3 smd rect (at 1.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 4 smd rect (at 2.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 139 /sdram/DQ1))
    (pad 5 smd rect (at 3.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 140 /sdram/DQ2))
    (pad 6 smd rect (at 4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 7 smd rect (at 4.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 141 /sdram/DQ3))
    (pad 8 smd rect (at 5.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 142 /sdram/DQ4))
    (pad 9 smd rect (at 6.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 10 smd rect (at 7.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 143 /sdram/DQ5))
    (pad 11 smd rect (at 8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 144 /sdram/DQ6))
    (pad 12 smd rect (at 8.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 13 smd rect (at 9.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 145 /sdram/DQ7))
    (pad 14 smd rect (at 10.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 15 smd rect (at 11.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 146 /sdram/DQML))
    (pad 16 smd rect (at 12 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 147 /sdram/WE))
    (pad 17 smd rect (at 12.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 148 /sdram/CAS))
    (pad 18 smd rect (at 13.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 149 /sdram/RAS))
    (pad 19 smd rect (at 14.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 150 /sdram/CS))
    (pad 20 smd rect (at 15.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 151 /sdram/BA0))
    (pad 21 smd rect (at 16 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 152 /sdram/BA1))
    (pad 22 smd rect (at 16.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 153 /sdram/A10))
    (pad 23 smd rect (at 17.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 154 /sdram/A0))
    (pad 24 smd rect (at 18.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 155 /sdram/A1))
    (pad 25 smd rect (at 19.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 156 /sdram/A2))
    (pad 26 smd rect (at 20 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 157 /sdram/A3))
    (pad 27 smd rect (at 20.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 28 smd rect (at 20.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 29 smd rect (at 20 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 158 /sdram/A4))
    (pad 30 smd rect (at 19.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 159 /sdram/A5))
    (pad 31 smd rect (at 18.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 160 /sdram/A6))
    (pad 32 smd rect (at 17.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 161 /sdram/A7))
    (pad 33 smd rect (at 16.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 162 /sdram/A8))
    (pad 34 smd rect (at 16 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 163 /sdram/A9))
    (pad 35 smd rect (at 15.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 164 /sdram/A11))
    (pad 36 smd rect (at 14.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 165 "Net-(U7-Pad36)"))
    (pad 37 smd rect (at 13.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 166 /sdram/CKE))
    (pad 38 smd rect (at 12.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 167 /sdram/CLK))
    (pad 39 smd rect (at 12 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 168 /sdram/DQMH))
    (pad 40 smd rect (at 11.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 169 "Net-(U7-Pad40)"))
    (pad 41 smd rect (at 10.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 42 smd rect (at 9.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 170 /sdram/DQ8))
    (pad 43 smd rect (at 8.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 44 smd rect (at 8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 171 /sdram/DQ9))
    (pad 45 smd rect (at 7.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 172 /sdram/DQ10))
    (pad 46 smd rect (at 6.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 47 smd rect (at 5.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 173 /sdram/DQ11))
    (pad 48 smd rect (at 4.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 174 /sdram/DQ12))
    (pad 49 smd rect (at 4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 50 smd rect (at 3.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 175 /sdram/DQ13))
    (pad 51 smd rect (at 2.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 176 /sdram/DQ14))
    (pad 52 smd rect (at 1.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 53 smd rect (at 0.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 177 /sdram/DQ15))
    (pad 54 smd rect (at 0 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
  )

  (module Housings_QFP:LQFP-100_14x14mm_Pitch0.5mm (layer F.Cu) (tedit 54130A77) (tstamp 56C4508F)
    (at 77.793728 84.329542 180)
    (descr "LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm (see NXP sot407-1_po.pdf and sot407-1_fr.pdf)")
    (tags "QFP 0.5")
    (path /563244F7/56C476C3)
    (attr smd)
    (fp_text reference U4 (at 0 -9.65 180) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value STM32F407VGT (at 0 9.65 180) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start -8.9 -8.9) (end -8.9 8.9) (layer F.CrtYd) (width 0.05))
    (fp_line (start 8.9 -8.9) (end 8.9 8.9) (layer F.CrtYd) (width 0.05))
    (fp_line (start -8.9 -8.9) (end 8.9 -8.9) (layer F.CrtYd) (width 0.05))
    (fp_line (start -8.9 8.9) (end 8.9 8.9) (layer F.CrtYd) (width 0.05))
    (fp_line (start -7.125 -7.125) (end -7.125 -6.365) (layer F.SilkS) (width 0.15))
    (fp_line (start 7.125 -7.125) (end 7.125 -6.365) (layer F.SilkS) (width 0.15))
    (fp_line (start 7.125 7.125) (end 7.125 6.365) (layer F.SilkS) (width 0.15))
    (fp_line (start -7.125 7.125) (end -7.125 6.365) (layer F.SilkS) (width 0.15))
    (fp_line (start -7.125 -7.125) (end -6.365 -7.125) (layer F.SilkS) (width 0.15))
    (fp_line (start -7.125 7.125) (end -6.365 7.125) (layer F.SilkS) (width 0.15))
    (fp_line (start 7.125 7.125) (end 6.365 7.125) (layer F.SilkS) (width 0.15))
    (fp_line (start 7.125 -7.125) (end 6.365 -7.125) (layer F.SilkS) (width 0.15))
    (fp_line (start -7.125 -6.365) (end -8.65 -6.365) (layer F.SilkS) (width 0.15))
    (pad 1 smd rect (at -7.9 -6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 13 /FSMC/A23))
    (pad 2 smd rect (at -7.9 -5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 14 /FSMC/A19))
    (pad 3 smd rect (at -7.9 -5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 15 /FSMC/A20))
    (pad 4 smd rect (at -7.9 -4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 16 /FSMC/A21))
    (pad 5 smd rect (at -7.9 -4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 17 /FSMC/A22))
    (pad 6 smd rect (at -7.9 -3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 7 smd rect (at -7.9 -3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 18 "Net-(U4-Pad7)"))
    (pad 8 smd rect (at -7.9 -2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 19 "Net-(U4-Pad8)"))
    (pad 9 smd rect (at -7.9 -2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 20 "Net-(U4-Pad9)"))
    (pad 10 smd rect (at -7.9 -1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 11 smd rect (at -7.9 -1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 12 smd rect (at -7.9 -0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 97 "Net-(C40-Pad1)"))
    (pad 13 smd rect (at -7.9 0 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 98 "Net-(C41-Pad1)"))
    (pad 14 smd rect (at -7.9 0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 21 "Net-(U4-Pad14)"))
    (pad 15 smd rect (at -7.9 1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 22 "Net-(U4-Pad15)"))
    (pad 16 smd rect (at -7.9 1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 23 "Net-(U4-Pad16)"))
    (pad 17 smd rect (at -7.9 2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 24 "Net-(U4-Pad17)"))
    (pad 18 smd rect (at -7.9 2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 25 "Net-(U4-Pad18)"))
    (pad 19 smd rect (at -7.9 3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 20 smd rect (at -7.9 3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 21 smd rect (at -7.9 4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 22 smd rect (at -7.9 4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 23 smd rect (at -7.9 5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 26 "Net-(U4-Pad23)"))
    (pad 24 smd rect (at -7.9 5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 27 "Net-(U4-Pad24)"))
    (pad 25 smd rect (at -7.9 6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 28 "Net-(U4-Pad25)"))
    (pad 26 smd rect (at -6 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 29 "Net-(U4-Pad26)"))
    (pad 27 smd rect (at -5.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 28 smd rect (at -5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 29 smd rect (at -4.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 30 "Net-(U4-Pad29)"))
    (pad 30 smd rect (at -4 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 31 "Net-(U4-Pad30)"))
    (pad 31 smd rect (at -3.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 32 "Net-(U4-Pad31)"))
    (pad 32 smd rect (at -3 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 33 "Net-(U4-Pad32)"))
    (pad 33 smd rect (at -2.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 34 "Net-(U4-Pad33)"))
    (pad 34 smd rect (at -2 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 35 "Net-(U4-Pad34)"))
    (pad 35 smd rect (at -1.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 36 "Net-(U4-Pad35)"))
    (pad 36 smd rect (at -1 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 37 "Net-(U4-Pad36)"))
    (pad 37 smd rect (at -0.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 38 /FSMC/BOOT1))
    (pad 38 smd rect (at 0 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 39 /FSMC/DA4))
    (pad 39 smd rect (at 0.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 40 /FSMC/DA5))
    (pad 40 smd rect (at 1 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 41 /FSMC/DA6))
    (pad 41 smd rect (at 1.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 42 /FSMC/DA7))
    (pad 42 smd rect (at 2 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 43 /FSMC/DA8))
    (pad 43 smd rect (at 2.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 44 /FSMC/DA9))
    (pad 44 smd rect (at 3 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 45 /FSMC/DA10))
    (pad 45 smd rect (at 3.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 46 /FSMC/DA11))
    (pad 46 smd rect (at 4 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 47 /FSMC/DA12))
    (pad 47 smd rect (at 4.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 48 "Net-(U4-Pad47)"))
    (pad 48 smd rect (at 5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 49 "Net-(U4-Pad48)"))
    (pad 49 smd rect (at 5.5 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 95 /powersupply/VCAP1))
    (pad 50 smd rect (at 6 7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 51 smd rect (at 7.9 6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 50 "Net-(U4-Pad51)"))
    (pad 52 smd rect (at 7.9 5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 51 "Net-(U4-Pad52)"))
    (pad 53 smd rect (at 7.9 5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 52 "Net-(U4-Pad53)"))
    (pad 54 smd rect (at 7.9 4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 53 "Net-(U4-Pad54)"))
    (pad 55 smd rect (at 7.9 4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 1 /FSMC/DA13))
    (pad 56 smd rect (at 7.9 3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 54 /FSMC/DA14))
    (pad 57 smd rect (at 7.9 3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 55 /FSMC/DA15))
    (pad 58 smd rect (at 7.9 2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 56 /FSMC/A16))
    (pad 59 smd rect (at 7.9 2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 57 /FSMC/A17))
    (pad 60 smd rect (at 7.9 1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 58 /FSMC/A18))
    (pad 61 smd rect (at 7.9 1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 59 /FSMC/DA0))
    (pad 62 smd rect (at 7.9 0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 60 /FSMC/DA1))
    (pad 63 smd rect (at 7.9 0 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 61 "Net-(U4-Pad63)"))
    (pad 64 smd rect (at 7.9 -0.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 62 "Net-(U4-Pad64)"))
    (pad 65 smd rect (at 7.9 -1 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 63 "Net-(U4-Pad65)"))
    (pad 66 smd rect (at 7.9 -1.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 64 "Net-(U4-Pad66)"))
    (pad 67 smd rect (at 7.9 -2 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 65 "Net-(U4-Pad67)"))
    (pad 68 smd rect (at 7.9 -2.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 66 "Net-(U4-Pad68)"))
    (pad 69 smd rect (at 7.9 -3 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 67 "Net-(U4-Pad69)"))
    (pad 70 smd rect (at 7.9 -3.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 68 "Net-(U4-Pad70)"))
    (pad 71 smd rect (at 7.9 -4 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 69 "Net-(U4-Pad71)"))
    (pad 72 smd rect (at 7.9 -4.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 70 "Net-(U4-Pad72)"))
    (pad 73 smd rect (at 7.9 -5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 96 /powersupply/VCAP2))
    (pad 74 smd rect (at 7.9 -5.5 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 75 smd rect (at 7.9 -6 180) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 76 smd rect (at 6 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 71 "Net-(U4-Pad76)"))
    (pad 77 smd rect (at 5.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 72 "Net-(U4-Pad77)"))
    (pad 78 smd rect (at 5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 73 "Net-(U4-Pad78)"))
    (pad 79 smd rect (at 4.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 74 "Net-(U4-Pad79)"))
    (pad 80 smd rect (at 4 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 75 "Net-(U4-Pad80)"))
    (pad 81 smd rect (at 3.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 76 /FSMC/DA2))
    (pad 82 smd rect (at 3 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 77 /FSMC/DA3))
    (pad 83 smd rect (at 2.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 78 "Net-(U4-Pad83)"))
    (pad 84 smd rect (at 2 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 79 /FSMC/CLK))
    (pad 85 smd rect (at 1.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 80 /FSMC/OE_N))
    (pad 86 smd rect (at 1 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 81 /FSMC/WE_N))
    (pad 87 smd rect (at 0.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 82 /FSMC/WAIT_N))
    (pad 88 smd rect (at 0 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 2 /FSMC/E1_N))
    (pad 89 smd rect (at -0.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 83 /FSMC/JTDO))
    (pad 90 smd rect (at -1 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 84 /FSMC/JRST_N))
    (pad 91 smd rect (at -1.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 85 "Net-(U4-Pad91)"))
    (pad 92 smd rect (at -2 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 86 "Net-(U4-Pad92)"))
    (pad 93 smd rect (at -2.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 87 /FSMC/ADV_N))
    (pad 94 smd rect (at -3 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 88 "Net-(U4-Pad94)"))
    (pad 95 smd rect (at -3.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 89 "Net-(U4-Pad95)"))
    (pad 96 smd rect (at -4 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 90 "Net-(U4-Pad96)"))
    (pad 97 smd rect (at -4.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 91 /FSMC/BL0_N))
    (pad 98 smd rect (at -5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 92 /FSMC/BL1_N))
    (pad 99 smd rect (at -5.5 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 100 smd rect (at -6 -7.9 270) (size 1.5 0.28) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (model Housings_QFP.3dshapes/LQFP-100_14x14mm_Pitch0.5mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm (layer F.Cu) (tedit 54130A77) (tstamp 56C45027)
    (at 73.543728 58.395542 180)
    (descr "144-Lead Plastic Low Profile Quad Flatpack (PL) - 20x20x1.40 mm Body [LQFP], 2.00 mm Footprint (see Microchip Packaging Specification 00000049BS.pdf)")
    (tags "QFP 0.5")
    (path /563244F7/56323459)
    (attr smd)
    (fp_text reference U3 (at 0 -12.475 180) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value LFXP2-5E-6TN144C (at 0 12.475 180) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start -11.75 -11.75) (end -11.75 11.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start 11.75 -11.75) (end 11.75 11.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -11.75 -11.75) (end 11.75 -11.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -11.75 11.75) (end 11.75 11.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -10.175 -10.175) (end -10.175 -9.125) (layer F.SilkS) (width 0.15))
    (fp_line (start 10.175 -10.175) (end 10.175 -9.125) (layer F.SilkS) (width 0.15))
    (fp_line (start 10.175 10.175) (end 10.175 9.125) (layer F.SilkS) (width 0.15))
    (fp_line (start -10.175 10.175) (end -10.175 9.125) (layer F.SilkS) (width 0.15))
    (fp_line (start -10.175 -10.175) (end -9.125 -10.175) (layer F.SilkS) (width 0.15))
    (fp_line (start -10.175 10.175) (end -9.125 10.175) (layer F.SilkS) (width 0.15))
    (fp_line (start 10.175 10.175) (end 9.125 10.175) (layer F.SilkS) (width 0.15))
    (fp_line (start 10.175 -10.175) (end 9.125 -10.175) (layer F.SilkS) (width 0.15))
    (fp_line (start -10.175 -9.125) (end -11.475 -9.125) (layer F.SilkS) (width 0.15))
    (pad 1 smd rect (at -10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 178 "Net-(U3-Pad1)"))
    (pad 2 smd rect (at -10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 179 "Net-(U3-Pad2)"))
    (pad 3 smd rect (at -10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 4 smd rect (at -10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 5 smd rect (at -10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 180 "Net-(U3-Pad5)"))
    (pad 6 smd rect (at -10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 181 "Net-(U3-Pad6)"))
    (pad 7 smd rect (at -10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 182 "Net-(U3-Pad7)"))
    (pad 8 smd rect (at -10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 183 "Net-(U3-Pad8)"))
    (pad 9 smd rect (at -10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 184 "Net-(U3-Pad9)"))
    (pad 10 smd rect (at -10.7 -4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 185 "Net-(U3-Pad10)"))
    (pad 11 smd rect (at -10.7 -3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 186 "Net-(U3-Pad11)"))
    (pad 12 smd rect (at -10.7 -3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 13 smd rect (at -10.7 -2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 187 "Net-(U3-Pad13)"))
    (pad 14 smd rect (at -10.7 -2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 15 smd rect (at -10.7 -1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 188 "Net-(U3-Pad15)"))
    (pad 16 smd rect (at -10.7 -1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 189 "Net-(U3-Pad16)"))
    (pad 17 smd rect (at -10.7 -0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 190 "Net-(U3-Pad17)"))
    (pad 18 smd rect (at -10.7 -0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 191 "Net-(U3-Pad18)"))
    (pad 19 smd rect (at -10.7 0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 158 /sdram/A4))
    (pad 20 smd rect (at -10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 159 /sdram/A5))
    (pad 21 smd rect (at -10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 160 /sdram/A6))
    (pad 22 smd rect (at -10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 161 /sdram/A7))
    (pad 23 smd rect (at -10.7 2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 24 smd rect (at -10.7 2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 6 +1V2))
    (pad 25 smd rect (at -10.7 3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 7 "Net-(R2-Pad2)"))
    (pad 26 smd rect (at -10.7 3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 8 "Net-(R3-Pad2)"))
    (pad 27 smd rect (at -10.7 4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 162 /sdram/A8))
    (pad 28 smd rect (at -10.7 4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 163 /sdram/A9))
    (pad 29 smd rect (at -10.7 5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 164 /sdram/A11))
    (pad 30 smd rect (at -10.7 5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 157 /sdram/A3))
    (pad 31 smd rect (at -10.7 6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 156 /sdram/A2))
    (pad 32 smd rect (at -10.7 6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 155 /sdram/A1))
    (pad 33 smd rect (at -10.7 7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 34 smd rect (at -10.7 7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 35 smd rect (at -10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 153 /sdram/A10))
    (pad 36 smd rect (at -10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 154 /sdram/A0))
    (pad 37 smd rect (at -8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 152 /sdram/BA1))
    (pad 38 smd rect (at -8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 151 /sdram/BA0))
    (pad 39 smd rect (at -7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 150 /sdram/CS))
    (pad 40 smd rect (at -7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 149 /sdram/RAS))
    (pad 41 smd rect (at -6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 42 smd rect (at -6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 43 smd rect (at -5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 166 /sdram/CKE))
    (pad 44 smd rect (at -5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 148 /sdram/CAS))
    (pad 45 smd rect (at -4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 167 /sdram/CLK))
    (pad 46 smd rect (at -4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 147 /sdram/WE))
    (pad 47 smd rect (at -3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 168 /sdram/DQMH))
    (pad 48 smd rect (at -3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 146 /sdram/DQML))
    (pad 49 smd rect (at -2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 50 smd rect (at -2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 145 /sdram/DQ7))
    (pad 51 smd rect (at -1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 52 smd rect (at -1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 170 /sdram/DQ8))
    (pad 53 smd rect (at -0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 144 /sdram/DQ6))
    (pad 54 smd rect (at -0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 171 /sdram/DQ9))
    (pad 55 smd rect (at 0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 143 /sdram/DQ5))
    (pad 56 smd rect (at 0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 172 /sdram/DQ10))
    (pad 57 smd rect (at 1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 142 /sdram/DQ4))
    (pad 58 smd rect (at 1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 173 /sdram/DQ11))
    (pad 59 smd rect (at 2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 6 +1V2))
    (pad 60 smd rect (at 2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 61 smd rect (at 3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 141 /sdram/DQ3))
    (pad 62 smd rect (at 3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 174 /sdram/DQ12))
    (pad 63 smd rect (at 4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 64 smd rect (at 4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 65 smd rect (at 5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 140 /sdram/DQ2))
    (pad 66 smd rect (at 5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 175 /sdram/DQ13))
    (pad 67 smd rect (at 6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 68 smd rect (at 6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 69 smd rect (at 7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 139 /sdram/DQ1))
    (pad 70 smd rect (at 7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 176 /sdram/DQ14))
    (pad 71 smd rect (at 8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 138 /sdram/DQ0))
    (pad 72 smd rect (at 8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 177 /sdram/DQ15))
    (pad 73 smd rect (at 10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 127 "Net-(U3-Pad73)"))
    (pad 74 smd rect (at 10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 106 /display/DB0))
    (pad 75 smd rect (at 10.7 7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 76 smd rect (at 10.7 7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 77 smd rect (at 10.7 6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 107 /display/DB1))
    (pad 78 smd rect (at 10.7 6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 108 /display/DB2))
    (pad 79 smd rect (at 10.7 5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 9 "Net-(P3-Pad3)"))
    (pad 80 smd rect (at 10.7 5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 10 "Net-(P3-Pad5)"))
    (pad 81 smd rect (at 10.7 4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 11 "Net-(P3-Pad1)"))
    (pad 82 smd rect (at 10.7 4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 12 "Net-(P3-Pad7)"))
    (pad 83 smd rect (at 10.7 3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 93 VSTM33))
    (pad 84 smd rect (at 10.7 3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 6 +1V2))
    (pad 85 smd rect (at 10.7 2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 86 smd rect (at 10.7 2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 87 smd rect (at 10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 109 /display/RS))
    (pad 88 smd rect (at 10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 110 /display/DB3))
    (pad 89 smd rect (at 10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 111 /display/WR))
    (pad 90 smd rect (at 10.7 0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 112 /display/DB4))
    (pad 91 smd rect (at 10.7 -0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 113 /display/RD))
    (pad 92 smd rect (at 10.7 -0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 114 /display/DB5))
    (pad 93 smd rect (at 10.7 -1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 115 /display/DB8))
    (pad 94 smd rect (at 10.7 -1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 116 /display/DB6))
    (pad 95 smd rect (at 10.7 -2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 96 smd rect (at 10.7 -2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 117 /display/DB9))
    (pad 97 smd rect (at 10.7 -3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 98 smd rect (at 10.7 -3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 118 /display/DB7))
    (pad 99 smd rect (at 10.7 -4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 119 /display/DB10))
    (pad 100 smd rect (at 10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 120 /display/DB11))
    (pad 101 smd rect (at 10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 121 /display/DB12))
    (pad 102 smd rect (at 10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 122 /display/DB13))
    (pad 103 smd rect (at 10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 123 /display/DB14))
    (pad 104 smd rect (at 10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 124 /display/DB15))
    (pad 105 smd rect (at 10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 106 smd rect (at 10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 107 smd rect (at 10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 125 /display/CS))
    (pad 108 smd rect (at 10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 126 /display/RST))
    (pad 109 smd rect (at 8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 87 /FSMC/ADV_N))
    (pad 110 smd rect (at 8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 2 /FSMC/E1_N))
    (pad 111 smd rect (at 7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 112 smd rect (at 7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 113 smd rect (at 6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 82 /FSMC/WAIT_N))
    (pad 114 smd rect (at 6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 81 /FSMC/WE_N))
    (pad 115 smd rect (at 5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 80 /FSMC/OE_N))
    (pad 116 smd rect (at 5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 79 /FSMC/CLK))
    (pad 117 smd rect (at 4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 118 smd rect (at 4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 6 +1V2))
    (pad 119 smd rect (at 3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 60 /FSMC/DA1))
    (pad 120 smd rect (at 3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 59 /FSMC/DA0))
    (pad 121 smd rect (at 2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 76 /FSMC/DA2))
    (pad 122 smd rect (at 2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 77 /FSMC/DA3))
    (pad 123 smd rect (at 1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 55 /FSMC/DA15))
    (pad 124 smd rect (at 1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 54 /FSMC/DA14))
    (pad 125 smd rect (at 0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 1 /FSMC/DA13))
    (pad 126 smd rect (at 0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 127 smd rect (at -0.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 47 /FSMC/DA12))
    (pad 128 smd rect (at -0.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 129 smd rect (at -1.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 46 /FSMC/DA11))
    (pad 130 smd rect (at -1.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 45 /FSMC/DA10))
    (pad 131 smd rect (at -2.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 44 /FSMC/DA9))
    (pad 132 smd rect (at -2.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 43 /FSMC/DA8))
    (pad 133 smd rect (at -3.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 42 /FSMC/DA7))
    (pad 134 smd rect (at -3.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 41 /FSMC/DA6))
    (pad 135 smd rect (at -4.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 94 GND))
    (pad 136 smd rect (at -4.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 137 smd rect (at -5.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 40 /FSMC/DA5))
    (pad 138 smd rect (at -5.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 39 /FSMC/DA4))
    (pad 139 smd rect (at -6.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (pad 140 smd rect (at -6.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 141 smd rect (at -7.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 56 /FSMC/A16))
    (pad 142 smd rect (at -7.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 57 /FSMC/A17))
    (pad 143 smd rect (at -8.25 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 58 /FSMC/A18))
    (pad 144 smd rect (at -8.75 -10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
      (net 14 /FSMC/A19))
    (model Housings_QFP.3dshapes/LQFP-144_20x20mm_Pitch0.5mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module TO_SOT_Packages_SMD:SOT-223 (layer F.Cu) (tedit 0) (tstamp 56C44F93)
    (at 104.648 84.582 270)
    (descr "module CMS SOT223 4 pins")
    (tags "CMS SOT")
    (path /563244F7/5632574B)
    (attr smd)
    (fp_text reference U1 (at 0 -0.762 270) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value LD1117S12CTR (at 0 0.762 270) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start -3.556 1.524) (end -3.556 4.572) (layer F.SilkS) (width 0.15))
    (fp_line (start -3.556 4.572) (end 3.556 4.572) (layer F.SilkS) (width 0.15))
    (fp_line (start 3.556 4.572) (end 3.556 1.524) (layer F.SilkS) (width 0.15))
    (fp_line (start -3.556 -1.524) (end -3.556 -2.286) (layer F.SilkS) (width 0.15))
    (fp_line (start -3.556 -2.286) (end -2.032 -4.572) (layer F.SilkS) (width 0.15))
    (fp_line (start -2.032 -4.572) (end 2.032 -4.572) (layer F.SilkS) (width 0.15))
    (fp_line (start 2.032 -4.572) (end 3.556 -2.286) (layer F.SilkS) (width 0.15))
    (fp_line (start 3.556 -2.286) (end 3.556 -1.524) (layer F.SilkS) (width 0.15))
    (pad 4 smd rect (at 0 -3.302 270) (size 3.6576 2.032) (layers F.Cu F.Paste F.Mask))
    (pad 2 smd rect (at 0 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask)
      (net 3 "Net-(C4-Pad1)"))
    (pad 3 smd rect (at 2.286 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 1 smd rect (at -2.286 3.302 270) (size 1.016 2.032) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (model TO_SOT_Packages_SMD.3dshapes/SOT-223.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.4 0.4 0.4))
      (rotate (xyz 0 0 0))
    )
  )

  (module itead-display:ITDB02-3.2WD (layer F.Cu) (tedit 56C6AB88) (tstamp 56C69EE3)
    (at 29 47.479)
    (path /563244F7/56C57ED6)
    (fp_text reference U6 (at -0.7 -6.575) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value ITDB02-3.2WD (at 9.3 -6.575) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text user 240px (at 77.1 23.225) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text user 400px (at 43.4 2.825) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text user 3.2" (at 44 22.525) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start 9.1 47.125) (end 80.1 1.225) (layer F.SilkS) (width 0.15))
    (fp_line (start 9.1 47.125) (end 9.1 1.225) (layer F.SilkS) (width 0.15))
    (fp_line (start 80.1 47.225) (end 9.1 47.125) (layer F.SilkS) (width 0.15))
    (fp_line (start 80.1 1.225) (end 80.1 47.225) (layer F.SilkS) (width 0.15))
    (fp_line (start 9.1 1.225) (end 80.1 1.225) (layer F.SilkS) (width 0.15))
    (fp_line (start -2.9 54.025) (end -2.9 -5.775) (layer F.SilkS) (width 0.15))
    (fp_line (start 92.1 54.025) (end -2.9 54.025) (layer F.SilkS) (width 0.15))
    (fp_line (start 92.1 -5.775) (end 92.1 54.025) (layer F.SilkS) (width 0.15))
    (fp_line (start -2.9 -5.775) (end 92.1 -5.775) (layer F.SilkS) (width 0.15))
    (fp_line (start -1.75 -1.7504) (end -1.75 50.0496) (layer F.CrtYd) (width 0.05))
    (fp_line (start 4.3 -1.7504) (end 4.3 50.0496) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.75 -1.7504) (end 4.3 -1.7504) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.75 50.0496) (end 4.3 50.0496) (layer F.CrtYd) (width 0.05))
    (fp_line (start 3.81 49.5296) (end 3.81 -1.2704) (layer F.SilkS) (width 0.15))
    (fp_line (start -1.27 1.2696) (end -1.27 49.5296) (layer F.SilkS) (width 0.15))
    (fp_line (start 3.81 49.5296) (end -1.27 49.5296) (layer F.SilkS) (width 0.15))
    (fp_line (start 3.81 -1.2704) (end 1.27 -1.2704) (layer F.SilkS) (width 0.15))
    (fp_line (start 0 -1.5504) (end -1.55 -1.5504) (layer F.SilkS) (width 0.15))
    (fp_line (start 1.27 -1.2704) (end 1.27 1.2696) (layer F.SilkS) (width 0.15))
    (fp_line (start 1.27 1.2696) (end -1.27 1.2696) (layer F.SilkS) (width 0.15))
    (fp_line (start -1.55 -1.5504) (end -1.55 -0.0004) (layer F.SilkS) (width 0.15))
    (pad 1 thru_hole rect (at 0 -0.0004) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 5 GNDD))
    (pad 2 thru_hole oval (at 2.54 -0.0004) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 106 /display/DB0))
    (pad 3 thru_hole oval (at 0 2.5396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 4 VFPGA33))
    (pad 4 thru_hole oval (at 2.54 2.5396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 107 /display/DB1))
    (pad 5 thru_hole oval (at 0 5.0796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 99 "Net-(U6-Pad5)"))
    (pad 6 thru_hole oval (at 2.54 5.0796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 108 /display/DB2))
    (pad 7 thru_hole oval (at 0 7.6196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 109 /display/RS))
    (pad 8 thru_hole oval (at 2.54 7.6196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 110 /display/DB3))
    (pad 9 thru_hole oval (at 0 10.1596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 111 /display/WR))
    (pad 10 thru_hole oval (at 2.54 10.1596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 112 /display/DB4))
    (pad 11 thru_hole oval (at 0 12.6996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 113 /display/RD))
    (pad 12 thru_hole oval (at 2.54 12.6996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 114 /display/DB5))
    (pad 13 thru_hole oval (at 0 15.2396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 115 /display/DB8))
    (pad 14 thru_hole oval (at 2.54 15.2396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 116 /display/DB6))
    (pad 15 thru_hole oval (at 0 17.7796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 117 /display/DB9))
    (pad 16 thru_hole oval (at 2.54 17.7796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 118 /display/DB7))
    (pad 17 thru_hole oval (at 0 20.3196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 119 /display/DB10))
    (pad 18 thru_hole oval (at 2.54 20.3196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 128 /display/T_CLK))
    (pad 19 thru_hole oval (at 0 22.8596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 120 /display/DB11))
    (pad 20 thru_hole oval (at 2.54 22.8596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 129 /display/T_CS))
    (pad 21 thru_hole oval (at 0 25.3996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 121 /display/DB12))
    (pad 22 thru_hole oval (at 2.54 25.3996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 130 /display/T_DIN))
    (pad 23 thru_hole oval (at 0 27.9396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 122 /display/DB13))
    (pad 24 thru_hole oval (at 2.54 27.9396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 131 /display/T_BUSY))
    (pad 25 thru_hole oval (at 0 30.4796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 123 /display/DB14))
    (pad 26 thru_hole oval (at 2.54 30.4796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 132 /display/T_DOUT))
    (pad 27 thru_hole oval (at 0 33.0196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 124 /display/DB15))
    (pad 28 thru_hole oval (at 2.54 33.0196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 133 /display/T_IRQ))
    (pad 29 thru_hole oval (at 0 35.5596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 125 /display/CS))
    (pad 30 thru_hole oval (at 2.54 35.5596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 134 /display/SD_SO))
    (pad 31 thru_hole oval (at 0 38.0996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 100 "Net-(U6-Pad31)"))
    (pad 32 thru_hole oval (at 2.54 38.0996) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 135 /display/SD_SCK))
    (pad 33 thru_hole oval (at 0 40.6396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 126 /display/RST))
    (pad 34 thru_hole oval (at 2.54 40.6396) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 136 /display/SD_SI))
    (pad 35 thru_hole oval (at 0 43.1796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 101 "Net-(U6-Pad35)"))
    (pad 36 thru_hole oval (at 2.54 43.1796) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 137 /display/SD_NSS))
    (pad 37 thru_hole oval (at 0 45.7196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 102 "Net-(R14-Pad1)"))
    (pad 38 thru_hole oval (at 2.54 45.7196) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 103 "Net-(U6-Pad38)"))
    (pad 39 thru_hole oval (at 0 48.2596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 104 "Net-(U6-Pad39)"))
    (pad 40 thru_hole oval (at 2.54 48.2596) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
      (net 105 "Net-(U6-Pad40)"))
    (pad "" np_thru_hole circle (at 9.1 -2.775) (size 7 7) (drill 3) (layers *.Cu *.Mask F.SilkS))
    (pad "" np_thru_hole circle (at 9.1 51.025) (size 7 7) (drill 3) (layers *.Cu *.Mask F.SilkS))
    (pad "" np_thru_hole circle (at 80.1 -2.775) (size 7 7) (drill 3) (layers *.Cu *.Mask F.SilkS))
    (pad "" np_thru_hole circle (at 80.1 51.025) (size 7 7) (drill 3) (layers *.Cu *.Mask F.SilkS))
    (model Pin_Headers.3dshapes/Pin_Header_Straight_2x20.wrl
      (at (xyz 0.05 -0.95 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 90))
    )
  )

  (module Capacitors_SMD:C_0603 (layer F.Cu) (tedit 5415D631) (tstamp 56C6B203)
    (at 66.802 64.516)
    (descr "Capacitor SMD 0603, reflow soldering, AVX (see smccp.pdf)")
    (tags "capacitor 0603")
    (path /563244F7/563274E4)
    (attr smd)
    (fp_text reference C12 (at 0 -1.9) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value 100n (at 0 1.9) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start -1.45 -0.75) (end 1.45 -0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.45 0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.45 -0.75) (end -1.45 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start 1.45 -0.75) (end 1.45 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
    (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
    (pad 1 smd rect (at -0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 2 smd rect (at 0.75 0) (size 0.8 0.75) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (model Capacitors_SMD.3dshapes/C_0603.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 56C6B209)
    (at 70.247442 64.516)
    (descr "Capacitor SMD 0603, hand soldering")
    (tags "capacitor 0603")
    (path /563244F7/56326CB4)
    (attr smd)
    (fp_text reference C13 (at 0 -1.9) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value 100n (at 0 1.9) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
    (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
    (pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 6 +1V2))
    (pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 56C6E945)
    (at 121.005888 53.176694)
    (descr "Capacitor SMD 0603, hand soldering")
    (tags "capacitor 0603")
    (path /563244F7/56C786E8)
    (attr smd)
    (fp_text reference C46 (at 0 -1.9) (layer F.SilkS)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_text value 100n (at 0 1.9) (layer F.Fab)
      (effects (font (size 1 1) (thickness 0.15)))
    )
    (fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
    (fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
    (fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
    (pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 4 VFPGA33))
    (pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
      (net 5 GNDD))
    (model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )

  (segment (start 68.914227 74.088229) (end 68.914227 80.253041) (width 0.153) (layer F.Cu) (net 1))
  (segment (start 68.914227 80.253041) (end 68.990728 80.329542) (width 0.153) (layer F.Cu) (net 1))
  (segment (start 68.990728 80.329542) (end 69.893728 80.329542) (width 0.153) (layer F.Cu) (net 1))
  (segment (start 68.914227 74.088229) (end 72.793728 70.208728) (width 0.153) (layer F.Cu) (net 1))
  (segment (start 72.793728 70.208728) (end 72.793728 69.095542) (width 0.153) (layer F.Cu) (net 1))
  (segment (start 67.103739 72.856342) (end 65.297728 71.050331) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 77.797728 94.183095) (end 76.447741 95.533082) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 67.103739 93.304009) (end 67.103739 72.856342) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 69.332812 95.533082) (end 67.103739 93.304009) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 65.297728 71.050331) (end 65.297728 70.483095) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 65.297728 70.483095) (end 65.297728 70.129542) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 77.797728 93.829542) (end 77.797728 94.183095) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 76.447741 95.533082) (end 69.332812 95.533082) (width 0.153) (layer B.Cu) (net 2))
  (segment (start 77.793728 92.261542) (end 77.793728 93.825542) (width 0.153) (layer F.Cu) (net 2))
  (segment (start 77.793728 93.825542) (end 77.797728 93.829542) (width 0.153) (layer F.Cu) (net 2))
  (via (at 77.797728 93.829542) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 2))
  (segment (start 65.293728 69.095542) (end 65.293728 70.125542) (width 0.153) (layer F.Cu) (net 2))
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