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Redesign of SDRAM IF

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This commit is contained in:
Markus Koch 2016-02-19 14:20:06 +01:00
parent 9eb3271030
commit 4d8add7ebe
11 changed files with 1415 additions and 1265 deletions
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43
FSMC.sch
View File

@ -1,4 +1,5 @@
EESchema Schematic File Version 2
LIBS:fpgna-rescue
LIBS:power
LIBS:device
LIBS:transistors
@ -212,10 +213,10 @@ F 3 "" H 5950 6900 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR68
L GND #PWR84
U 1 1 56C67B1F
P 5400 7200
F 0 "#PWR68" H 5400 6950 50 0001 C CNN
F 0 "#PWR84" H 5400 6950 50 0001 C CNN
F 1 "GND" H 5408 7026 50 0000 C CNN
F 2 "" H 5400 7200 50 0000 C CNN
F 3 "" H 5400 7200 50 0000 C CNN
@ -223,10 +224,10 @@ F 3 "" H 5400 7200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR69
L GND #PWR85
U 1 1 56C67B55
P 5600 7200
F 0 "#PWR69" H 5600 6950 50 0001 C CNN
F 0 "#PWR85" H 5600 6950 50 0001 C CNN
F 1 "GND" H 5608 7026 50 0000 C CNN
F 2 "" H 5600 7200 50 0000 C CNN
F 3 "" H 5600 7200 50 0000 C CNN
@ -234,10 +235,10 @@ F 3 "" H 5600 7200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR71
L GND #PWR87
U 1 1 56C67C80
P 5850 7200
F 0 "#PWR71" H 5850 6950 50 0001 C CNN
F 0 "#PWR87" H 5850 6950 50 0001 C CNN
F 1 "GND" H 5858 7026 50 0000 C CNN
F 2 "" H 5850 7200 50 0000 C CNN
F 3 "" H 5850 7200 50 0000 C CNN
@ -256,10 +257,10 @@ F 3 "" H 3800 7000 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR67
L GND #PWR83
U 1 1 56C680A6
P 4000 7200
F 0 "#PWR67" H 4000 6950 50 0001 C CNN
F 0 "#PWR83" H 4000 6950 50 0001 C CNN
F 1 "GND" H 4008 7026 50 0000 C CNN
F 2 "" H 4000 7200 50 0000 C CNN
F 3 "" H 4000 7200 50 0000 C CNN
@ -267,10 +268,10 @@ F 3 "" H 4000 7200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR66
L GND #PWR82
U 1 1 56C6815E
P 3800 7200
F 0 "#PWR66" H 3800 6950 50 0001 C CNN
F 0 "#PWR82" H 3800 6950 50 0001 C CNN
F 1 "GND" H 3808 7026 50 0000 C CNN
F 2 "" H 3800 7200 50 0000 C CNN
F 3 "" H 3800 7200 50 0000 C CNN
@ -475,10 +476,10 @@ A18
Text Label 5750 6300 2 60 ~ 0
A19
$Comp
L VFPGA33 #PWR72
L VFPGA33 #PWR88
U 1 1 56C6B01D
P 5950 6650
F 0 "#PWR72" H 5950 6500 50 0001 C CNN
F 0 "#PWR88" H 5950 6500 50 0001 C CNN
F 1 "VFPGA33" H 5968 6824 50 0000 C CNN
F 2 "" H 5950 6650 50 0000 C CNN
F 3 "" H 5950 6650 50 0000 C CNN
@ -486,10 +487,10 @@ F 3 "" H 5950 6650 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR70
L VFPGA33 #PWR86
U 1 1 56C6B114
P 5750 6550
F 0 "#PWR70" H 5750 6400 50 0001 C CNN
F 0 "#PWR86" H 5750 6400 50 0001 C CNN
F 1 "VFPGA33" H 5768 6724 50 0000 C CNN
F 2 "" H 5750 6550 50 0000 C CNN
F 3 "" H 5750 6550 50 0000 C CNN
@ -497,10 +498,10 @@ F 3 "" H 5750 6550 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR65
L VFPGA33 #PWR81
U 1 1 56C6B644
P 3800 6550
F 0 "#PWR65" H 3800 6400 50 0001 C CNN
F 0 "#PWR81" H 3800 6400 50 0001 C CNN
F 1 "VFPGA33" H 3818 6724 50 0000 C CNN
F 2 "" H 3800 6550 50 0000 C CNN
F 3 "" H 3800 6550 50 0000 C CNN
@ -523,7 +524,7 @@ Connection ~ 5750 6600
Wire Bus Line
2650 4200 3250 4200
Wire Bus Line
2900 4200 2900 4300
2900 4200 2900 4800
Wire Bus Line
2900 4300 2650 4300
Wire Bus Line
@ -532,4 +533,12 @@ Wire Bus Line
3250 700 3350 700
Text Notes 3400 750 0 118 ~ 0
TODO
Wire Bus Line
2900 4400 2650 4400
Wire Bus Line
2900 4600 2650 4600
Wire Bus Line
2900 4700 2650 4700
Wire Bus Line
2900 4800 2650 4800
$EndSCHEMATC

25
debug.sch
View File

@ -1,4 +1,5 @@
EESchema Schematic File Version 2
LIBS:fpgna-rescue
LIBS:power
LIBS:device
LIBS:transistors
@ -95,10 +96,10 @@ F 3 "" H 3750 1050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR61
L GNDD #PWR77
U 1 1 5633954D
P 3750 1300
F 0 "#PWR61" H 3750 1050 50 0001 C CNN
F 0 "#PWR77" H 3750 1050 50 0001 C CNN
F 1 "GNDD" H 3750 1150 50 0000 C CNN
F 2 "" H 3750 1300 60 0000 C CNN
F 3 "" H 3750 1300 60 0000 C CNN
@ -119,10 +120,10 @@ Wire Wire Line
Wire Wire Line
5150 1600 4900 1600
$Comp
L GNDD #PWR64
L GNDD #PWR80
U 1 1 568DA1F8
P 5150 1900
F 0 "#PWR64" H 5150 1650 50 0001 C CNN
F 0 "#PWR80" H 5150 1650 50 0001 C CNN
F 1 "GNDD" H 5150 1750 50 0000 C CNN
F 2 "" H 5150 1900 60 0000 C CNN
F 3 "" H 5150 1900 60 0000 C CNN
@ -160,10 +161,10 @@ JRST_N
Text HLabel 2450 3450 2 60 Output ~ 0
BOOT1
$Comp
L VSTM33 #PWR63
L VSTM33 #PWR79
U 1 1 56C71229
P 5150 1400
F 0 "#PWR63" H 5150 1250 50 0001 C CNN
F 0 "#PWR79" H 5150 1250 50 0001 C CNN
F 1 "VSTM33" H 5168 1574 50 0000 C CNN
F 2 "" H 5150 1400 50 0000 C CNN
F 3 "" H 5150 1400 50 0000 C CNN
@ -171,10 +172,10 @@ F 3 "" H 5150 1400 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSTM33 #PWR60
L VSTM33 #PWR76
U 1 1 56C71245
P 3550 800
F 0 "#PWR60" H 3550 650 50 0001 C CNN
F 0 "#PWR76" H 3550 650 50 0001 C CNN
F 1 "VSTM33" H 3568 974 50 0000 C CNN
F 2 "" H 3550 800 50 0000 C CNN
F 3 "" H 3550 800 50 0000 C CNN
@ -232,10 +233,10 @@ Wire Wire Line
1600 2900 1600 3550
Connection ~ 1700 2900
$Comp
L GND #PWR59
L GND #PWR75
U 1 1 56C718AB
P 1600 3550
F 0 "#PWR59" H 1600 3300 50 0001 C CNN
F 0 "#PWR75" H 1600 3300 50 0001 C CNN
F 1 "GND" H 1608 3376 50 0000 C CNN
F 2 "" H 1600 3550 50 0000 C CNN
F 3 "" H 1600 3550 50 0000 C CNN
@ -264,10 +265,10 @@ Wire Wire Line
Wire Wire Line
4850 3000 5050 3000
$Comp
L GND #PWR62
L GND #PWR78
U 1 1 56C74066
P 5000 3150
F 0 "#PWR62" H 5000 2900 50 0001 C CNN
F 0 "#PWR78" H 5000 2900 50 0001 C CNN
F 1 "GND" H 5008 2976 50 0000 C CNN
F 2 "" H 5000 3150 50 0000 C CNN
F 3 "" H 5000 3150 50 0000 C CNN

29
display.sch
View File

@ -1,4 +1,5 @@
EESchema Schematic File Version 2
LIBS:fpgna-rescue
LIBS:power
LIBS:device
LIBS:transistors
@ -349,10 +350,10 @@ F 3 "" H 3250 7150 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR75
L GND #PWR91
U 1 1 56C62B6C
P 2700 7450
F 0 "#PWR75" H 2700 7200 50 0001 C CNN
F 0 "#PWR91" H 2700 7200 50 0001 C CNN
F 1 "GND" H 2708 7276 50 0000 C CNN
F 2 "" H 2700 7450 50 0000 C CNN
F 3 "" H 2700 7450 50 0000 C CNN
@ -360,10 +361,10 @@ F 3 "" H 2700 7450 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR76
L GND #PWR92
U 1 1 56C62B72
P 2900 7450
F 0 "#PWR76" H 2900 7200 50 0001 C CNN
F 0 "#PWR92" H 2900 7200 50 0001 C CNN
F 1 "GND" H 2908 7276 50 0000 C CNN
F 2 "" H 2900 7450 50 0000 C CNN
F 3 "" H 2900 7450 50 0000 C CNN
@ -371,10 +372,10 @@ F 3 "" H 2900 7450 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR78
L GND #PWR94
U 1 1 56C62B78
P 3150 7450
F 0 "#PWR78" H 3150 7200 50 0001 C CNN
F 0 "#PWR94" H 3150 7200 50 0001 C CNN
F 1 "GND" H 3158 7276 50 0000 C CNN
F 2 "" H 3150 7450 50 0000 C CNN
F 3 "" H 3150 7450 50 0000 C CNN
@ -393,10 +394,10 @@ Wire Wire Line
3150 7450 3150 7300
Connection ~ 3150 7300
$Comp
L VFPGA33 #PWR79
L VFPGA33 #PWR95
U 1 1 56C62B84
P 3250 6900
F 0 "#PWR79" H 3250 6750 50 0001 C CNN
F 0 "#PWR95" H 3250 6750 50 0001 C CNN
F 1 "VFPGA33" H 3268 7074 50 0000 C CNN
F 2 "" H 3250 6900 50 0000 C CNN
F 3 "" H 3250 6900 50 0000 C CNN
@ -404,10 +405,10 @@ F 3 "" H 3250 6900 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR77
L VFPGA33 #PWR93
U 1 1 56C62B8A
P 3050 6800
F 0 "#PWR77" H 3050 6650 50 0001 C CNN
F 0 "#PWR93" H 3050 6650 50 0001 C CNN
F 1 "VFPGA33" H 3068 6974 50 0000 C CNN
F 2 "" H 3050 6800 50 0000 C CNN
F 3 "" H 3050 6800 50 0000 C CNN
@ -440,10 +441,10 @@ $EndComp
Wire Wire Line
1150 7050 1350 7050
$Comp
L VFPGA33 #PWR73
L VFPGA33 #PWR89
U 1 1 56C62DAA
P 1150 7000
F 0 "#PWR73" H 1150 6850 50 0001 C CNN
F 0 "#PWR89" H 1150 6850 50 0001 C CNN
F 1 "VFPGA33" H 1168 7174 50 0000 C CNN
F 2 "" H 1150 7000 50 0000 C CNN
F 3 "" H 1150 7000 50 0000 C CNN
@ -462,10 +463,10 @@ Wire Wire Line
1250 7400 1250 7450
Connection ~ 1250 7400
$Comp
L GND #PWR74
L GND #PWR90
U 1 1 56C62F03
P 1250 7450
F 0 "#PWR74" H 1250 7200 50 0001 C CNN
F 0 "#PWR90" H 1250 7200 50 0001 C CNN
F 1 "GND" H 1258 7276 50 0000 C CNN
F 2 "" H 1250 7450 50 0000 C CNN
F 3 "" H 1250 7450 50 0000 C CNN

6
fpgna-cache.lib
View File

@ -228,11 +228,11 @@ X 2 2 0 -300 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# IS42S16800F
# IS42S16800F-RESCUE-fpgna
#
DEF IS42S16800F U 0 40 Y Y 4 L N
DEF IS42S16800F-RESCUE-fpgna U 0 40 Y Y 4 L N
F0 "U" 250 150 60 H V C CNN
F1 "IS42S16800F" 300 50 60 H V C CNN
F1 "IS42S16800F-RESCUE-fpgna" 300 50 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW

73
fpgna-rescue.lib Normal file
View File

@ -0,0 +1,73 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# IS42S16800F-RESCUE-fpgna
#
DEF IS42S16800F-RESCUE-fpgna U 0 40 Y Y 4 L N
F0 "U" 250 150 60 H V C CNN
F1 "IS42S16800F-RESCUE-fpgna" 300 50 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S 0 0 550 -850 1 1 0 f
X VDD 1 -200 -100 200 R 50 50 1 1 W
X VDDQ 3 -200 -450 200 R 50 50 1 1 W
X VSSQ 6 750 -450 200 L 50 50 1 1 W
X VDDQ 9 -200 -550 200 R 50 50 1 1 W
X VSS 41 750 -200 200 L 50 50 1 1 W
X VSSQ 12 750 -550 200 L 50 50 1 1 W
X VSSQ 52 750 -750 200 L 50 50 1 1 W
X VDDQ 43 -200 -650 200 R 50 50 1 1 W
X VDD 14 -200 -200 200 R 50 50 1 1 W
X VSS 54 750 -300 200 L 50 50 1 1 W
X VSSQ 46 750 -650 200 L 50 50 1 1 W
X VDD 27 -200 -300 200 R 50 50 1 1 W
X VSS 28 750 -100 200 L 50 50 1 1 W
X VDDQ 49 -200 -750 200 R 50 50 1 1 W
S 0 0 550 -1700 2 1 0 f
X DQ0 2 -200 -100 200 R 50 50 2 1 B
X DQ1 4 -200 -200 200 R 50 50 2 1 B
X DQ2 5 -200 -300 200 R 50 50 2 1 B
X DQ3 7 -200 -400 200 R 50 50 2 1 B
X DQ4 8 -200 -500 200 R 50 50 2 1 B
X DQ5 10 -200 -600 200 R 50 50 2 1 B
X BA0 20 750 -1500 200 L 50 50 2 1 I
X A5 30 750 -600 200 L 50 50 2 1 I
X DQ13 50 -200 -1400 200 R 50 50 2 1 B
X DQ6 11 -200 -700 200 R 50 50 2 1 B
X BA1 21 750 -1600 200 L 50 50 2 1 I
X A6 31 750 -700 200 L 50 50 2 1 I
X DQ14 51 -200 -1500 200 R 50 50 2 1 B
X A10 22 750 -1100 200 L 50 50 2 1 I
X A7 32 750 -800 200 L 50 50 2 1 I
X DQ8 42 -200 -900 200 R 50 50 2 1 B
X DQ7 13 -200 -800 200 R 50 50 2 1 B
X A0 23 750 -100 200 L 50 50 2 1 I
X A8 33 750 -900 200 L 50 50 2 1 I
X DQ15 53 -200 -1600 200 R 50 50 2 1 B
X A1 24 750 -200 200 L 50 50 2 1 I
X A9 34 750 -1000 200 L 50 50 2 1 I
X DQ9 44 -200 -1000 200 R 50 50 2 1 B
X A2 25 750 -300 200 L 50 50 2 1 I
X A11 35 750 -1200 200 L 50 50 2 1 I
X DQ10 45 -200 -1100 200 R 50 50 2 1 B
X A3 26 750 -400 200 L 50 50 2 1 I
X DQ11 47 -200 -1200 200 R 50 50 2 1 B
X DQ12 48 -200 -1300 200 R 50 50 2 1 B
X A4 29 750 -500 200 L 50 50 2 1 I
S 0 0 550 -700 3 1 0 f
X DQML 15 750 -200 200 L 50 50 3 1 I
X WE 16 -200 -600 200 R 50 50 3 1 I I
X CAS 17 -200 -500 200 R 50 50 3 1 I I
X CKE 37 -200 -200 200 R 50 50 3 1 I
X RAS 18 -200 -400 200 R 50 50 3 1 I I
X CLK 38 -200 -100 200 R 50 50 3 1 I C
X CS 19 -200 -300 200 R 50 50 3 1 I I
X DQMH 39 750 -100 200 L 50 50 3 1 I
S 0 0 550 -300 4 1 0 f
X NC 40 -200 -200 200 R 50 50 4 1 N
X NC 36 -200 -100 200 R 50 50 4 1 N
ENDDRAW
ENDDEF
#
#End Library

652
fpgna.kicad_pcb
View File

@ -2,11 +2,11 @@
(general
(links 156)
(no_connects 86)
(area 25.871999 39.826 123.114841 102.157)
(no_connects 78)
(area 25.871999 29.997 123.114841 102.157)
(thickness 1.6)
(drawings 0)
(tracks 445)
(tracks 485)
(zones 0)
(modules 8)
(nets 192)
@ -267,20 +267,20 @@
(net 175 /sdram/DQ13)
(net 176 /sdram/DQ14)
(net 177 /sdram/DQ15)
(net 178 "Net-(U3-Pad53)")
(net 179 "Net-(U3-Pad54)")
(net 180 "Net-(U3-Pad55)")
(net 181 "Net-(U3-Pad56)")
(net 182 "Net-(U3-Pad57)")
(net 183 "Net-(U3-Pad58)")
(net 184 "Net-(U3-Pad61)")
(net 185 "Net-(U3-Pad62)")
(net 186 "Net-(U3-Pad65)")
(net 187 "Net-(U3-Pad66)")
(net 188 "Net-(U3-Pad69)")
(net 189 "Net-(U3-Pad70)")
(net 190 "Net-(U3-Pad71)")
(net 191 "Net-(U3-Pad72)")
(net 178 "Net-(U3-Pad1)")
(net 179 "Net-(U3-Pad2)")
(net 180 "Net-(U3-Pad5)")
(net 181 "Net-(U3-Pad6)")
(net 182 "Net-(U3-Pad7)")
(net 183 "Net-(U3-Pad8)")
(net 184 "Net-(U3-Pad9)")
(net 185 "Net-(U3-Pad10)")
(net 186 "Net-(U3-Pad11)")
(net 187 "Net-(U3-Pad13)")
(net 188 "Net-(U3-Pad15)")
(net 189 "Net-(U3-Pad16)")
(net 190 "Net-(U3-Pad17)")
(net 191 "Net-(U3-Pad18)")
(net_class Default "This is the default net class."
(clearance 0.153)
@ -408,21 +408,21 @@
(add_net "Net-(R14-Pad1)")
(add_net "Net-(R2-Pad2)")
(add_net "Net-(R3-Pad2)")
(add_net "Net-(U3-Pad53)")
(add_net "Net-(U3-Pad54)")
(add_net "Net-(U3-Pad55)")
(add_net "Net-(U3-Pad56)")
(add_net "Net-(U3-Pad57)")
(add_net "Net-(U3-Pad58)")
(add_net "Net-(U3-Pad61)")
(add_net "Net-(U3-Pad62)")
(add_net "Net-(U3-Pad65)")
(add_net "Net-(U3-Pad66)")
(add_net "Net-(U3-Pad69)")
(add_net "Net-(U3-Pad70)")
(add_net "Net-(U3-Pad71)")
(add_net "Net-(U3-Pad72)")
(add_net "Net-(U3-Pad1)")
(add_net "Net-(U3-Pad10)")
(add_net "Net-(U3-Pad11)")
(add_net "Net-(U3-Pad13)")
(add_net "Net-(U3-Pad15)")
(add_net "Net-(U3-Pad16)")
(add_net "Net-(U3-Pad17)")
(add_net "Net-(U3-Pad18)")
(add_net "Net-(U3-Pad2)")
(add_net "Net-(U3-Pad5)")
(add_net "Net-(U3-Pad6)")
(add_net "Net-(U3-Pad7)")
(add_net "Net-(U3-Pad73)")
(add_net "Net-(U3-Pad8)")
(add_net "Net-(U3-Pad9)")
(add_net "Net-(U4-Pad14)")
(add_net "Net-(U4-Pad15)")
(add_net "Net-(U4-Pad16)")
@ -483,12 +483,12 @@
)
(module smd:TSOP-54 (layer F.Cu) (tedit 56C6D015) (tstamp 56C6E984)
(at 102.8 67.9 90)
(at 66.8 42.9)
(path /563244F7/56C702B2)
(fp_text reference U7 (at -1.9 -6.5 180) (layer F.SilkS)
(fp_text reference U7 (at -1.9 -6.5 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value IS42S16800F (at 10.05 -5.8 90) (layer F.Fab)
(fp_text value IS42S16800F (at 10.05 -5.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0.323502 -2) (end 0.55 -1.6) (layer F.SilkS) (width 0.15))
@ -496,113 +496,113 @@
(fp_line (start 21.5 -0.95) (end 21.5 -11.05) (layer F.SilkS) (width 0.15))
(fp_line (start -0.7 -0.95) (end 21.5 -0.95) (layer F.SilkS) (width 0.15))
(fp_line (start -0.7 -11.05) (end -0.7 -0.95) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at 0 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 1 smd rect (at 0 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 2 smd rect (at 0.8 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 2 smd rect (at 0.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 138 /sdram/DQ0))
(pad 3 smd rect (at 1.6 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 3 smd rect (at 1.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 4 smd rect (at 2.4 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 4 smd rect (at 2.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 139 /sdram/DQ1))
(pad 5 smd rect (at 3.2 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 5 smd rect (at 3.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 140 /sdram/DQ2))
(pad 6 smd rect (at 4 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 6 smd rect (at 4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 7 smd rect (at 4.8 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 7 smd rect (at 4.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 141 /sdram/DQ3))
(pad 8 smd rect (at 5.6 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 8 smd rect (at 5.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 142 /sdram/DQ4))
(pad 9 smd rect (at 6.4 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 9 smd rect (at 6.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 10 smd rect (at 7.2 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 10 smd rect (at 7.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 143 /sdram/DQ5))
(pad 11 smd rect (at 8 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 11 smd rect (at 8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 144 /sdram/DQ6))
(pad 12 smd rect (at 8.8 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 12 smd rect (at 8.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 13 smd rect (at 9.6 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 13 smd rect (at 9.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 145 /sdram/DQ7))
(pad 14 smd rect (at 10.4 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 14 smd rect (at 10.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 15 smd rect (at 11.2 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 15 smd rect (at 11.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 146 /sdram/DQML))
(pad 16 smd rect (at 12 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 16 smd rect (at 12 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 147 /sdram/WE))
(pad 17 smd rect (at 12.8 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 17 smd rect (at 12.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 148 /sdram/CAS))
(pad 18 smd rect (at 13.6 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 18 smd rect (at 13.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 149 /sdram/RAS))
(pad 19 smd rect (at 14.4 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 19 smd rect (at 14.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 150 /sdram/CS))
(pad 20 smd rect (at 15.2 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 20 smd rect (at 15.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 151 /sdram/BA0))
(pad 21 smd rect (at 16 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 21 smd rect (at 16 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 152 /sdram/BA1))
(pad 22 smd rect (at 16.8 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 22 smd rect (at 16.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 153 /sdram/A10))
(pad 23 smd rect (at 17.6 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 23 smd rect (at 17.6 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 154 /sdram/A0))
(pad 24 smd rect (at 18.4 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 24 smd rect (at 18.4 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 155 /sdram/A1))
(pad 25 smd rect (at 19.2 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 25 smd rect (at 19.2 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 156 /sdram/A2))
(pad 26 smd rect (at 20 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 26 smd rect (at 20 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 157 /sdram/A3))
(pad 27 smd rect (at 20.8 0 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 27 smd rect (at 20.8 0) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 28 smd rect (at 20.8 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 28 smd rect (at 20.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 29 smd rect (at 20 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 29 smd rect (at 20 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 158 /sdram/A4))
(pad 30 smd rect (at 19.2 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 30 smd rect (at 19.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 159 /sdram/A5))
(pad 31 smd rect (at 18.4 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 31 smd rect (at 18.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 160 /sdram/A6))
(pad 32 smd rect (at 17.6 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 32 smd rect (at 17.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 161 /sdram/A7))
(pad 33 smd rect (at 16.8 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 33 smd rect (at 16.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 162 /sdram/A8))
(pad 34 smd rect (at 16 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 34 smd rect (at 16 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 163 /sdram/A9))
(pad 35 smd rect (at 15.2 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 35 smd rect (at 15.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 164 /sdram/A11))
(pad 36 smd rect (at 14.4 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 36 smd rect (at 14.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 165 "Net-(U7-Pad36)"))
(pad 37 smd rect (at 13.6 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 37 smd rect (at 13.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 166 /sdram/CKE))
(pad 38 smd rect (at 12.8 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 38 smd rect (at 12.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 167 /sdram/CLK))
(pad 39 smd rect (at 12 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 39 smd rect (at 12 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 168 /sdram/DQMH))
(pad 40 smd rect (at 11.2 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 40 smd rect (at 11.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 169 "Net-(U7-Pad40)"))
(pad 41 smd rect (at 10.4 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 41 smd rect (at 10.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 42 smd rect (at 9.6 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 42 smd rect (at 9.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 170 /sdram/DQ8))
(pad 43 smd rect (at 8.8 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 43 smd rect (at 8.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 44 smd rect (at 8 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 44 smd rect (at 8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 171 /sdram/DQ9))
(pad 45 smd rect (at 7.2 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 45 smd rect (at 7.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 172 /sdram/DQ10))
(pad 46 smd rect (at 6.4 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 46 smd rect (at 6.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 47 smd rect (at 5.6 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 47 smd rect (at 5.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 173 /sdram/DQ11))
(pad 48 smd rect (at 4.8 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 48 smd rect (at 4.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 174 /sdram/DQ12))
(pad 49 smd rect (at 4 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 49 smd rect (at 4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 50 smd rect (at 3.2 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 50 smd rect (at 3.2 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 175 /sdram/DQ13))
(pad 51 smd rect (at 2.4 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 51 smd rect (at 2.4 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 176 /sdram/DQ14))
(pad 52 smd rect (at 1.6 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 52 smd rect (at 1.6 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 53 smd rect (at 0.8 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 53 smd rect (at 0.8 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 177 /sdram/DQ15))
(pad 54 smd rect (at 0 -12 90) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(pad 54 smd rect (at 0 -12) (size 0.55 1.5) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
)
@ -864,49 +864,49 @@
(fp_line (start 10.175 -10.175) (end 9.125 -10.175) (layer F.SilkS) (width 0.15))
(fp_line (start -10.175 -9.125) (end -11.475 -9.125) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -10.7 -8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 177 /sdram/DQ15))
(net 178 "Net-(U3-Pad1)"))
(pad 2 smd rect (at -10.7 -8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 138 /sdram/DQ0))
(net 179 "Net-(U3-Pad2)"))
(pad 3 smd rect (at -10.7 -7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 94 GND))
(pad 4 smd rect (at -10.7 -7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 5 smd rect (at -10.7 -6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 176 /sdram/DQ14))
(net 180 "Net-(U3-Pad5)"))
(pad 6 smd rect (at -10.7 -6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 139 /sdram/DQ1))
(net 181 "Net-(U3-Pad6)"))
(pad 7 smd rect (at -10.7 -5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 175 /sdram/DQ13))
(net 182 "Net-(U3-Pad7)"))
(pad 8 smd rect (at -10.7 -5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 140 /sdram/DQ2))
(net 183 "Net-(U3-Pad8)"))
(pad 9 smd rect (at -10.7 -4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 174 /sdram/DQ12))
(net 184 "Net-(U3-Pad9)"))
(pad 10 smd rect (at -10.7 -4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 141 /sdram/DQ3))
(net 185 "Net-(U3-Pad10)"))
(pad 11 smd rect (at -10.7 -3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 173 /sdram/DQ11))
(net 186 "Net-(U3-Pad11)"))
(pad 12 smd rect (at -10.7 -3.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 94 GND))
(pad 13 smd rect (at -10.7 -2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 142 /sdram/DQ4))
(net 187 "Net-(U3-Pad13)"))
(pad 14 smd rect (at -10.7 -2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 15 smd rect (at -10.7 -1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 172 /sdram/DQ10))
(net 188 "Net-(U3-Pad15)"))
(pad 16 smd rect (at -10.7 -1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 143 /sdram/DQ5))
(net 189 "Net-(U3-Pad16)"))
(pad 17 smd rect (at -10.7 -0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 171 /sdram/DQ9))
(net 190 "Net-(U3-Pad17)"))
(pad 18 smd rect (at -10.7 -0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 144 /sdram/DQ6))
(net 191 "Net-(U3-Pad18)"))
(pad 19 smd rect (at -10.7 0.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 170 /sdram/DQ8))
(net 158 /sdram/A4))
(pad 20 smd rect (at -10.7 0.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 145 /sdram/DQ7))
(net 159 /sdram/A5))
(pad 21 smd rect (at -10.7 1.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 146 /sdram/DQML))
(net 160 /sdram/A6))
(pad 22 smd rect (at -10.7 1.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 168 /sdram/DQMH))
(net 161 /sdram/A7))
(pad 23 smd rect (at -10.7 2.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 24 smd rect (at -10.7 2.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
@ -916,97 +916,97 @@
(pad 26 smd rect (at -10.7 3.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 8 "Net-(R3-Pad2)"))
(pad 27 smd rect (at -10.7 4.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 147 /sdram/WE))
(net 162 /sdram/A8))
(pad 28 smd rect (at -10.7 4.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 167 /sdram/CLK))
(net 163 /sdram/A9))
(pad 29 smd rect (at -10.7 5.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 148 /sdram/CAS))
(net 164 /sdram/A11))
(pad 30 smd rect (at -10.7 5.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 166 /sdram/CKE))
(net 157 /sdram/A3))
(pad 31 smd rect (at -10.7 6.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 149 /sdram/RAS))
(net 156 /sdram/A2))
(pad 32 smd rect (at -10.7 6.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 150 /sdram/CS))
(net 155 /sdram/A1))
(pad 33 smd rect (at -10.7 7.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 34 smd rect (at -10.7 7.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 94 GND))
(pad 35 smd rect (at -10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 151 /sdram/BA0))
(pad 36 smd rect (at -10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 152 /sdram/BA1))
(pad 37 smd rect (at -8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 164 /sdram/A11))
(pad 38 smd rect (at -8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 163 /sdram/A9))
(pad 39 smd rect (at -7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 162 /sdram/A8))
(pad 40 smd rect (at -7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 153 /sdram/A10))
(pad 36 smd rect (at -10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 154 /sdram/A0))
(pad 37 smd rect (at -8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 152 /sdram/BA1))
(pad 38 smd rect (at -8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 151 /sdram/BA0))
(pad 39 smd rect (at -7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 150 /sdram/CS))
(pad 40 smd rect (at -7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 149 /sdram/RAS))
(pad 41 smd rect (at -6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 94 GND))
(pad 42 smd rect (at -6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 43 smd rect (at -5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 161 /sdram/A7))
(net 166 /sdram/CKE))
(pad 44 smd rect (at -5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 154 /sdram/A0))
(net 148 /sdram/CAS))
(pad 45 smd rect (at -4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 160 /sdram/A6))
(net 167 /sdram/CLK))
(pad 46 smd rect (at -4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 155 /sdram/A1))
(net 147 /sdram/WE))
(pad 47 smd rect (at -3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 159 /sdram/A5))
(net 168 /sdram/DQMH))
(pad 48 smd rect (at -3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 156 /sdram/A2))
(net 146 /sdram/DQML))
(pad 49 smd rect (at -2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 50 smd rect (at -2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 158 /sdram/A4))
(net 145 /sdram/DQ7))
(pad 51 smd rect (at -1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 94 GND))
(pad 52 smd rect (at -1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 157 /sdram/A3))
(net 170 /sdram/DQ8))
(pad 53 smd rect (at -0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 178 "Net-(U3-Pad53)"))
(net 144 /sdram/DQ6))
(pad 54 smd rect (at -0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 179 "Net-(U3-Pad54)"))
(net 171 /sdram/DQ9))
(pad 55 smd rect (at 0.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 180 "Net-(U3-Pad55)"))
(net 143 /sdram/DQ5))
(pad 56 smd rect (at 0.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 181 "Net-(U3-Pad56)"))
(net 172 /sdram/DQ10))
(pad 57 smd rect (at 1.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 182 "Net-(U3-Pad57)"))
(net 142 /sdram/DQ4))
(pad 58 smd rect (at 1.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 183 "Net-(U3-Pad58)"))
(net 173 /sdram/DQ11))
(pad 59 smd rect (at 2.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 6 +1V2))
(pad 60 smd rect (at 2.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 61 smd rect (at 3.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 184 "Net-(U3-Pad61)"))
(net 141 /sdram/DQ3))
(pad 62 smd rect (at 3.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 185 "Net-(U3-Pad62)"))
(net 174 /sdram/DQ12))
(pad 63 smd rect (at 4.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 64 smd rect (at 4.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 94 GND))
(pad 65 smd rect (at 5.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 186 "Net-(U3-Pad65)"))
(net 140 /sdram/DQ2))
(pad 66 smd rect (at 5.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 187 "Net-(U3-Pad66)"))
(net 175 /sdram/DQ13))
(pad 67 smd rect (at 6.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 4 VFPGA33))
(pad 68 smd rect (at 6.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 5 GNDD))
(pad 69 smd rect (at 7.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 188 "Net-(U3-Pad69)"))
(net 139 /sdram/DQ1))
(pad 70 smd rect (at 7.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 189 "Net-(U3-Pad70)"))
(net 176 /sdram/DQ14))
(pad 71 smd rect (at 8.25 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 190 "Net-(U3-Pad71)"))
(net 138 /sdram/DQ0))
(pad 72 smd rect (at 8.75 10.7 270) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 191 "Net-(U3-Pad72)"))
(net 177 /sdram/DQ15))
(pad 73 smd rect (at 10.7 8.75 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
(net 127 "Net-(U3-Pad73)"))
(pad 74 smd rect (at 10.7 8.25 180) (size 1.55 0.3) (layers F.Cu F.Paste F.Mask)
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1050
fpgna.net
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File diff suppressed because it is too large Load Diff

77
fpgna.pro
View File

@ -1,4 +1,4 @@
update=Fri 19 Feb 2016 08:35:36 AM CET
update=Fri 19 Feb 2016 01:27:56 PM CET
version=1
last_client=kicad
[pcbnew]
@ -29,40 +29,41 @@ version=1
version=1
LibDir=../ShimattaPCBLibs/schematics
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
LibName30=Oscillators
LibName31=lattice/lattice
LibName32=power/pmic
LibName33=libs/specific-powersyms
LibName34=power/regulators
LibName35=stm/stm32f4
LibName36=shields/itead-displays
LibName37=memory/ram
LibName1=fpgna-rescue
LibName2=power
LibName3=device
LibName4=transistors
LibName5=conn
LibName6=linear
LibName7=regul
LibName8=74xx
LibName9=cmos4000
LibName10=adc-dac
LibName11=memory
LibName12=xilinx
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=Oscillators
LibName32=lattice/lattice
LibName33=power/pmic
LibName34=libs/specific-powersyms
LibName35=power/regulators
LibName36=stm/stm32f4
LibName37=shields/itead-displays
LibName38=memory/ram

1
fpgna.sch
View File

@ -1,4 +1,5 @@
EESchema Schematic File Version 2
LIBS:fpgna-rescue
LIBS:power
LIBS:device
LIBS:transistors

237
power.sch
View File

@ -1,4 +1,5 @@
EESchema Schematic File Version 2
LIBS:fpgna-rescue
LIBS:power
LIBS:device
LIBS:transistors
@ -65,10 +66,10 @@ F 5 "Makise Kurisu <kurisu@shimatta.de>" H 1800 6600 60 0001 C CNN "Author"
1 0 0 -1
$EndComp
$Comp
L +1V2 #PWR26
L +1V2 #PWR42
U 1 1 56323D6C
P 3950 4850
F 0 "#PWR26" H 3950 4700 50 0001 C CNN
F 0 "#PWR42" H 3950 4700 50 0001 C CNN
F 1 "+1V2" H 3950 4990 50 0000 C CNN
F 2 "" H 3950 4850 60 0000 C CNN
F 3 "" H 3950 4850 60 0000 C CNN
@ -76,10 +77,10 @@ F 3 "" H 3950 4850 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR25
L GNDD #PWR41
U 1 1 56323EF3
P 3900 6250
F 0 "#PWR25" H 3900 6000 50 0001 C CNN
F 0 "#PWR41" H 3900 6000 50 0001 C CNN
F 1 "GNDD" H 3900 6100 50 0000 C CNN
F 2 "" H 3900 6250 60 0000 C CNN
F 3 "" H 3900 6250 60 0000 C CNN
@ -87,10 +88,10 @@ F 3 "" H 3900 6250 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR33
L GNDD #PWR49
U 1 1 56323F5A
P 5350 4950
F 0 "#PWR33" H 5350 4700 50 0001 C CNN
F 0 "#PWR49" H 5350 4700 50 0001 C CNN
F 1 "GNDD" H 5350 4800 50 0000 C CNN
F 2 "" H 5350 4950 60 0000 C CNN
F 3 "" H 5350 4950 60 0000 C CNN
@ -153,10 +154,10 @@ F 3 "" H 3700 2050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR27
L GNDD #PWR43
U 1 1 56325A76
P 4250 2300
F 0 "#PWR27" H 4250 2050 50 0001 C CNN
F 0 "#PWR43" H 4250 2050 50 0001 C CNN
F 1 "GNDD" H 4250 2150 50 0000 C CNN
F 2 "" H 4250 2300 60 0000 C CNN
F 3 "" H 4250 2300 60 0000 C CNN
@ -186,10 +187,10 @@ F 3 "" H 5400 1850 60 0000 C CNN
0 -1 -1 0
$EndComp
$Comp
L +1V2 #PWR35
L +1V2 #PWR51
U 1 1 56325E26
P 5800 1750
F 0 "#PWR35" H 5800 1600 50 0001 C CNN
F 0 "#PWR51" H 5800 1600 50 0001 C CNN
F 1 "+1V2" H 5800 1890 50 0000 C CNN
F 2 "" H 5800 1750 60 0000 C CNN
F 3 "" H 5800 1750 60 0000 C CNN
@ -274,10 +275,10 @@ F 3 "" H 5500 4050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L +1V2 #PWR31
L +1V2 #PWR47
U 1 1 56326FC5
P 4750 3800
F 0 "#PWR31" H 4750 3650 50 0001 C CNN
F 0 "#PWR47" H 4750 3650 50 0001 C CNN
F 1 "+1V2" H 4750 3940 50 0000 C CNN
F 2 "" H 4750 3800 60 0000 C CNN
F 3 "" H 4750 3800 60 0000 C CNN
@ -285,10 +286,10 @@ F 3 "" H 4750 3800 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR32
L GNDD #PWR48
U 1 1 5632709B
P 4750 4300
F 0 "#PWR32" H 4750 4050 50 0001 C CNN
F 0 "#PWR48" H 4750 4050 50 0001 C CNN
F 1 "GNDD" H 4750 4150 50 0000 C CNN
F 2 "" H 4750 4300 60 0000 C CNN
F 3 "" H 4750 4300 60 0000 C CNN
@ -373,10 +374,10 @@ F 3 "" H 5250 3050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR30
L GNDD #PWR46
U 1 1 5632751F
P 4750 3300
F 0 "#PWR30" H 4750 3050 50 0001 C CNN
F 0 "#PWR46" H 4750 3050 50 0001 C CNN
F 1 "GNDD" H 4750 3150 50 0000 C CNN
F 2 "" H 4750 3300 60 0000 C CNN
F 3 "" H 4750 3300 60 0000 C CNN
@ -417,10 +418,10 @@ F 3 "" H 8700 5050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR53
L GNDD #PWR69
U 1 1 56329332
P 9500 5300
F 0 "#PWR53" H 9500 5050 50 0001 C CNN
F 0 "#PWR69" H 9500 5050 50 0001 C CNN
F 1 "GNDD" H 9500 5150 50 0000 C CNN
F 2 "" H 9500 5300 60 0000 C CNN
F 3 "" H 9500 5300 60 0000 C CNN
@ -441,10 +442,10 @@ F 3 "" V 7450 1050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR41
L GNDD #PWR57
U 1 1 56330682
P 7700 1500
F 0 "#PWR41" H 7700 1250 50 0001 C CNN
F 0 "#PWR57" H 7700 1250 50 0001 C CNN
F 1 "GNDD" H 7700 1350 50 0000 C CNN
F 2 "" H 7700 1500 60 0000 C CNN
F 3 "" H 7700 1500 60 0000 C CNN
@ -485,10 +486,10 @@ F 3 "" H 7750 3050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VUSB #PWR37
L VUSB #PWR53
U 1 1 56C1E573
P 7050 1200
F 0 "#PWR37" H 7050 1050 50 0001 C CNN
F 0 "#PWR53" H 7050 1050 50 0001 C CNN
F 1 "VUSB" H 7068 1374 50 0000 C CNN
F 2 "" H 7050 1200 50 0000 C CNN
F 3 "" H 7050 1200 50 0000 C CNN
@ -496,10 +497,10 @@ F 3 "" H 7050 1200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VBAT #PWR46
L VBAT #PWR62
U 1 1 56C1ED5D
P 8600 2750
F 0 "#PWR46" H 8600 2600 50 0001 C CNN
F 0 "#PWR62" H 8600 2600 50 0001 C CNN
F 1 "VBAT" H 8600 2890 50 0000 C CNN
F 2 "" H 8600 2750 50 0000 C CNN
F 3 "" H 8600 2750 50 0000 C CNN
@ -507,10 +508,10 @@ F 3 "" H 8600 2750 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VUSB #PWR39
L VUSB #PWR55
U 1 1 56C1F811
P 7500 2750
F 0 "#PWR39" H 7500 2600 50 0001 C CNN
F 0 "#PWR55" H 7500 2600 50 0001 C CNN
F 1 "VUSB" H 7500 2890 50 0000 C CNN
F 2 "" H 7500 2750 50 0000 C CNN
F 3 "" H 7500 2750 50 0000 C CNN
@ -534,10 +535,10 @@ F 4 "TODO: Verify pinout" H 10127 3150 60 0000 L CNN "TODO"
1 0 0 -1
$EndComp
$Comp
L VBAT #PWR57
L VBAT #PWR73
U 1 1 56C23113
P 9800 2750
F 0 "#PWR57" H 9800 2600 50 0001 C CNN
F 0 "#PWR73" H 9800 2600 50 0001 C CNN
F 1 "VBAT" H 9800 2890 50 0000 C CNN
F 2 "" H 9800 2750 50 0000 C CNN
F 3 "" H 9800 2750 50 0000 C CNN
@ -545,10 +546,10 @@ F 3 "" H 9800 2750 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR40
L GNDD #PWR56
U 1 1 56C23816
P 7500 3950
F 0 "#PWR40" H 7500 3700 50 0001 C CNN
F 0 "#PWR56" H 7500 3700 50 0001 C CNN
F 1 "GNDD" H 7500 3800 50 0000 C CNN
F 2 "" H 7500 3950 60 0000 C CNN
F 3 "" H 7500 3950 60 0000 C CNN
@ -556,10 +557,10 @@ F 3 "" H 7500 3950 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR58
L GNDD #PWR74
U 1 1 56C23E07
P 9800 3950
F 0 "#PWR58" H 9800 3700 50 0001 C CNN
F 0 "#PWR74" H 9800 3700 50 0001 C CNN
F 1 "GNDD" H 9800 3800 50 0000 C CNN
F 2 "" H 9800 3950 60 0000 C CNN
F 3 "" H 9800 3950 60 0000 C CNN
@ -578,10 +579,10 @@ F 3 "" H 8600 3700 30 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR47
L GNDD #PWR63
U 1 1 56C253CE
P 8600 3950
F 0 "#PWR47" H 8600 3700 50 0001 C CNN
F 0 "#PWR63" H 8600 3700 50 0001 C CNN
F 1 "GNDD" H 8600 3800 50 0000 C CNN
F 2 "" H 8600 3950 60 0000 C CNN
F 3 "" H 8600 3950 60 0000 C CNN
@ -589,10 +590,10 @@ F 3 "" H 8600 3950 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VUSB #PWR45
L VUSB #PWR61
U 1 1 56C2BB98
P 8600 950
F 0 "#PWR45" H 8600 800 50 0001 C CNN
F 0 "#PWR61" H 8600 800 50 0001 C CNN
F 1 "VUSB" H 8600 1090 50 0000 C CNN
F 2 "" H 8600 950 50 0000 C CNN
F 3 "" H 8600 950 50 0000 C CNN
@ -600,10 +601,10 @@ F 3 "" H 8600 950 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VBAT #PWR44
L VBAT #PWR60
U 1 1 56C2D4CD
P 8400 950
F 0 "#PWR44" H 8400 800 50 0001 C CNN
F 0 "#PWR60" H 8400 800 50 0001 C CNN
F 1 "VBAT" H 8400 1090 50 0000 C CNN
F 2 "" H 8400 950 50 0000 C CNN
F 3 "" H 8400 950 50 0000 C CNN
@ -633,10 +634,10 @@ F 3 "" H 8900 1950 30 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR49
L GNDD #PWR65
U 1 1 56C307A1
P 8900 2150
F 0 "#PWR49" H 8900 1900 50 0001 C CNN
F 0 "#PWR65" H 8900 1900 50 0001 C CNN
F 1 "GNDD" H 8900 2000 50 0000 C CNN
F 2 "" H 8900 2150 60 0000 C CNN
F 3 "" H 8900 2150 60 0000 C CNN
@ -655,10 +656,10 @@ F 3 "" V 8900 1050 50 0000 C CNN
-1 0 0 1
$EndComp
$Comp
L VSYS #PWR5
L VSYS #PWR21
U 1 1 56C39868
P 1000 1000
F 0 "#PWR5" H 1000 850 50 0001 C CNN
F 0 "#PWR21" H 1000 850 50 0001 C CNN
F 1 "VSYS" H 1000 1140 50 0000 C CNN
F 2 "" H 1000 1000 50 0000 C CNN
F 3 "" H 1000 1000 50 0000 C CNN
@ -666,10 +667,10 @@ F 3 "" H 1000 1000 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSYS #PWR52
L VSYS #PWR68
U 1 1 56C39AFF
P 9350 950
F 0 "#PWR52" H 9350 800 50 0001 C CNN
F 0 "#PWR68" H 9350 800 50 0001 C CNN
F 1 "VSYS" H 9350 1090 50 0000 C CNN
F 2 "" H 9350 950 50 0000 C CNN
F 3 "" H 9350 950 50 0000 C CNN
@ -688,10 +689,10 @@ F 3 "" H 7250 2950 30 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR48
L GNDD #PWR64
U 1 1 56C4E595
P 8850 3950
F 0 "#PWR48" H 8850 3700 50 0001 C CNN
F 0 "#PWR64" H 8850 3700 50 0001 C CNN
F 1 "GNDD" H 8850 3800 50 0000 C CNN
F 2 "" H 8850 3950 60 0000 C CNN
F 3 "" H 8850 3950 60 0000 C CNN
@ -699,10 +700,10 @@ F 3 "" H 8850 3950 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VUSB #PWR50
L VUSB #PWR66
U 1 1 56C4F548
P 9200 2750
F 0 "#PWR50" H 9200 2600 50 0001 C CNN
F 0 "#PWR66" H 9200 2600 50 0001 C CNN
F 1 "VUSB" H 9200 2890 50 0000 C CNN
F 2 "" H 9200 2750 50 0000 C CNN
F 3 "" H 9200 2750 50 0000 C CNN
@ -710,10 +711,10 @@ F 3 "" H 9200 2750 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR51
L GNDD #PWR67
U 1 1 56C4FA15
P 9200 3950
F 0 "#PWR51" H 9200 3700 50 0001 C CNN
F 0 "#PWR67" H 9200 3700 50 0001 C CNN
F 1 "GNDD" H 9200 3800 50 0000 C CNN
F 2 "" H 9200 3950 60 0000 C CNN
F 3 "" H 9200 3950 60 0000 C CNN
@ -754,10 +755,10 @@ F 3 "" H 9550 3750 30 0000 C CNN
-1 0 0 1
$EndComp
$Comp
L GNDD #PWR54
L GNDD #PWR70
U 1 1 56C59A2E
P 9550 3950
F 0 "#PWR54" H 9550 3700 50 0001 C CNN
F 0 "#PWR70" H 9550 3700 50 0001 C CNN
F 1 "GNDD" H 9550 3800 50 0000 C CNN
F 2 "" H 9550 3950 60 0000 C CNN
F 3 "" H 9550 3950 60 0000 C CNN
@ -789,10 +790,10 @@ F 3 "" H 9700 1550 30 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSYS #PWR55
L VSYS #PWR71
U 1 1 56C208D6
P 9700 950
F 0 "#PWR55" H 9700 800 50 0001 C CNN
F 0 "#PWR71" H 9700 800 50 0001 C CNN
F 1 "VSYS" H 9700 1090 50 0000 C CNN
F 2 "" H 9700 950 50 0000 C CNN
F 3 "" H 9700 950 50 0000 C CNN
@ -800,10 +801,10 @@ F 3 "" H 9700 950 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR56
L GNDD #PWR72
U 1 1 56C20CEB
P 9700 1800
F 0 "#PWR56" H 9700 1550 50 0001 C CNN
F 0 "#PWR72" H 9700 1550 50 0001 C CNN
F 1 "GNDD" H 9700 1650 50 0000 C CNN
F 2 "" H 9700 1800 60 0000 C CNN
F 3 "" H 9700 1800 60 0000 C CNN
@ -846,10 +847,10 @@ F 3 "" H 1500 1500 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR6
L GNDD #PWR22
U 1 1 56C35DE1
P 1000 1850
F 0 "#PWR6" H 1000 1600 50 0001 C CNN
F 0 "#PWR22" H 1000 1600 50 0001 C CNN
F 1 "GNDD" H 1000 1700 50 0000 C CNN
F 2 "" H 1000 1850 60 0000 C CNN
F 3 "" H 1000 1850 60 0000 C CNN
@ -857,10 +858,10 @@ F 3 "" H 1000 1850 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR9
L GNDD #PWR25
U 1 1 56C35F4F
P 1750 1850
F 0 "#PWR9" H 1750 1600 50 0001 C CNN
F 0 "#PWR25" H 1750 1600 50 0001 C CNN
F 1 "GNDD" H 1750 1700 50 0000 C CNN
F 2 "" H 1750 1850 60 0000 C CNN
F 3 "" H 1750 1850 60 0000 C CNN
@ -868,10 +869,10 @@ F 3 "" H 1750 1850 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR8
L GNDD #PWR24
U 1 1 56C360EB
P 1400 1850
F 0 "#PWR8" H 1400 1600 50 0001 C CNN
F 0 "#PWR24" H 1400 1600 50 0001 C CNN
F 1 "GNDD" H 1400 1700 50 0000 C CNN
F 2 "" H 1400 1850 60 0000 C CNN
F 3 "" H 1400 1850 60 0000 C CNN
@ -890,10 +891,10 @@ F 3 "" V 2100 1450 50 0000 C CNN
0 1 1 0
$EndComp
$Comp
L GNDD #PWR14
L GNDD #PWR30
U 1 1 56C2CFDF
P 2100 1850
F 0 "#PWR14" H 2100 1600 50 0001 C CNN
F 0 "#PWR30" H 2100 1600 50 0001 C CNN
F 1 "GNDD" H 2100 1700 50 0000 C CNN
F 2 "" H 2100 1850 60 0000 C CNN
F 3 "" H 2100 1850 60 0000 C CNN
@ -923,10 +924,10 @@ F 3 "" H 2850 1500 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR18
L GNDD #PWR34
U 1 1 56C2E498
P 2850 1850
F 0 "#PWR18" H 2850 1600 50 0001 C CNN
F 0 "#PWR34" H 2850 1600 50 0001 C CNN
F 1 "GNDD" H 2850 1700 50 0000 C CNN
F 2 "" H 2850 1850 60 0000 C CNN
F 3 "" H 2850 1850 60 0000 C CNN
@ -945,10 +946,10 @@ F 3 "" H 750 1400 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR1
L GNDD #PWR17
U 1 1 56C2F49B
P 750 1850
F 0 "#PWR1" H 750 1600 50 0001 C CNN
F 0 "#PWR17" H 750 1600 50 0001 C CNN
F 1 "GNDD" H 750 1700 50 0000 C CNN
F 2 "" H 750 1850 60 0000 C CNN
F 3 "" H 750 1850 60 0000 C CNN
@ -956,10 +957,10 @@ F 3 "" H 750 1850 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSTM33 #PWR19
L VSTM33 #PWR35
U 1 1 56C326BF
P 2950 1050
F 0 "#PWR19" H 2950 900 50 0001 C CNN
F 0 "#PWR35" H 2950 900 50 0001 C CNN
F 1 "VSTM33" H 2950 1190 50 0000 C CNN
F 2 "" H 2950 1050 50 0000 C CNN
F 3 "" H 2950 1050 50 0000 C CNN
@ -967,10 +968,10 @@ F 3 "" H 2950 1050 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR22
L VFPGA33 #PWR38
U 1 1 56C350CF
P 3700 1750
F 0 "#PWR22" H 3700 1600 50 0001 C CNN
F 0 "#PWR38" H 3700 1600 50 0001 C CNN
F 1 "VFPGA33" H 3700 1890 50 0000 C CNN
F 2 "" H 3700 1750 50 0000 C CNN
F 3 "" H 3700 1750 50 0000 C CNN
@ -989,10 +990,10 @@ F 3 "http://www.digikey.com/product-search/en/discrete-semiconductor-products/fe
0 1 -1 0
$EndComp
$Comp
L VSTM33 #PWR21
L VSTM33 #PWR37
U 1 1 56C36219
P 3700 950
F 0 "#PWR21" H 3700 800 50 0001 C CNN
F 0 "#PWR37" H 3700 800 50 0001 C CNN
F 1 "VSTM33" H 3700 1090 50 0000 C CNN
F 2 "" H 3700 950 50 0000 C CNN
F 3 "" H 3700 950 50 0000 C CNN
@ -1000,10 +1001,10 @@ F 3 "" H 3700 950 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR28
L VFPGA33 #PWR44
U 1 1 56C36471
P 4400 950
F 0 "#PWR28" H 4400 800 50 0001 C CNN
F 0 "#PWR44" H 4400 800 50 0001 C CNN
F 1 "VFPGA33" H 4400 1090 50 0000 C CNN
F 2 "" H 4400 950 50 0000 C CNN
F 3 "" H 4400 950 50 0000 C CNN
@ -1058,10 +1059,10 @@ F 3 "" H 1000 4200 60 0000 C CNN
$EndComp
NoConn ~ 7550 3250
$Comp
L GND #PWR15
L GND #PWR31
U 1 1 56C4E388
P 2200 5200
F 0 "#PWR15" H 2200 4950 50 0001 C CNN
F 0 "#PWR31" H 2200 4950 50 0001 C CNN
F 1 "GND" H 2208 5026 50 0000 C CNN
F 2 "" H 2200 5200 50 0000 C CNN
F 3 "" H 2200 5200 50 0000 C CNN
@ -1069,10 +1070,10 @@ F 3 "" H 2200 5200 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSTM33 #PWR38
L VSTM33 #PWR54
U 1 1 56C54669
P 7250 2750
F 0 "#PWR38" H 7250 2600 50 0001 C CNN
F 0 "#PWR54" H 7250 2600 50 0001 C CNN
F 1 "VSTM33" H 7250 2890 50 0000 C CNN
F 2 "" H 7250 2750 50 0000 C CNN
F 3 "" H 7250 2750 50 0000 C CNN
@ -1080,10 +1081,10 @@ F 3 "" H 7250 2750 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSTM33 #PWR7
L VSTM33 #PWR23
U 1 1 56C58A5C
P 1250 3450
F 0 "#PWR7" H 1250 3300 50 0001 C CNN
F 0 "#PWR23" H 1250 3300 50 0001 C CNN
F 1 "VSTM33" H 1250 3590 50 0000 C CNN
F 2 "" H 1250 3450 50 0000 C CNN
F 3 "" H 1250 3450 50 0000 C CNN
@ -1113,10 +1114,10 @@ F 3 "" H 800 5000 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GND #PWR4
L GND #PWR20
U 1 1 56C5D446
P 900 5200
F 0 "#PWR4" H 900 4950 50 0001 C CNN
F 0 "#PWR20" H 900 4950 50 0001 C CNN
F 1 "GND" H 908 5026 50 0000 C CNN
F 2 "" H 900 5200 50 0000 C CNN
F 3 "" H 900 5200 50 0000 C CNN
@ -1139,10 +1140,10 @@ VCAP1
Text Label 1000 4800 0 60 ~ 0
VCAP2
$Comp
L VFPGA33 #PWR29
L VFPGA33 #PWR45
U 1 1 56C4A0C6
P 4750 2800
F 0 "#PWR29" H 4750 2650 50 0001 C CNN
F 0 "#PWR45" H 4750 2650 50 0001 C CNN
F 1 "VFPGA33" H 4750 2940 50 0000 C CNN
F 2 "" H 4750 2800 50 0000 C CNN
F 3 "" H 4750 2800 50 0000 C CNN
@ -1227,10 +1228,10 @@ F 3 "" H 2750 2700 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR11
L GNDD #PWR27
U 1 1 56C506AD
P 1750 2950
F 0 "#PWR11" H 1750 2700 50 0001 C CNN
F 0 "#PWR27" H 1750 2700 50 0001 C CNN
F 1 "GNDD" H 1750 2800 50 0000 C CNN
F 2 "" H 1750 2950 60 0000 C CNN
F 3 "" H 1750 2950 60 0000 C CNN
@ -1238,10 +1239,10 @@ F 3 "" H 1750 2950 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VSTM33 #PWR10
L VSTM33 #PWR26
U 1 1 56C509AA
P 1750 2450
F 0 "#PWR10" H 1750 2300 50 0001 C CNN
F 0 "#PWR26" H 1750 2300 50 0001 C CNN
F 1 "VSTM33" H 1750 2590 50 0000 C CNN
F 2 "" H 1750 2450 50 0000 C CNN
F 3 "" H 1750 2450 50 0000 C CNN
@ -1699,10 +1700,10 @@ Wire Wire Line
Wire Wire Line
7950 1050 7900 1050
$Comp
L GNDD #PWR43
L GNDD #PWR59
U 1 1 56C5AF1C
P 7950 1500
F 0 "#PWR43" H 7950 1250 50 0001 C CNN
F 0 "#PWR59" H 7950 1250 50 0001 C CNN
F 1 "GNDD" H 7950 1350 50 0000 C CNN
F 2 "" H 7950 1500 60 0000 C CNN
F 3 "" H 7950 1500 60 0000 C CNN
@ -1736,10 +1737,10 @@ $EndComp
Wire Wire Line
3450 6850 4850 6850
$Comp
L GNDD #PWR20
L GNDD #PWR36
U 1 1 56C58F25
P 3650 7300
F 0 "#PWR20" H 3650 7050 50 0001 C CNN
F 0 "#PWR36" H 3650 7050 50 0001 C CNN
F 1 "GNDD" H 3650 7150 50 0000 C CNN
F 2 "" H 3650 7300 60 0000 C CNN
F 3 "" H 3650 7300 60 0000 C CNN
@ -1753,10 +1754,10 @@ Wire Wire Line
Wire Wire Line
5850 6850 5850 7300
$Comp
L GNDD #PWR36
L GNDD #PWR52
U 1 1 56C592D8
P 5850 7300
F 0 "#PWR36" H 5850 7050 50 0001 C CNN
F 0 "#PWR52" H 5850 7050 50 0001 C CNN
F 1 "GNDD" H 5850 7150 50 0000 C CNN
F 2 "" H 5850 7300 60 0000 C CNN
F 3 "" H 5850 7300 60 0000 C CNN
@ -1777,10 +1778,10 @@ $EndComp
Wire Wire Line
4450 7000 4500 7000
$Comp
L VFPGA33 #PWR24
L VFPGA33 #PWR40
U 1 1 56C61112
P 3850 6800
F 0 "#PWR24" H 3850 6650 50 0001 C CNN
F 0 "#PWR40" H 3850 6650 50 0001 C CNN
F 1 "VFPGA33" H 3868 6974 50 0000 C CNN
F 2 "" H 3850 6800 50 0000 C CNN
F 3 "" H 3850 6800 50 0000 C CNN
@ -1827,10 +1828,10 @@ $EndComp
Wire Wire Line
4850 7000 4800 7000
$Comp
L VFPGA33 #PWR34
L VFPGA33 #PWR50
U 1 1 56C69ECC
P 5550 4850
F 0 "#PWR34" H 5550 4700 50 0001 C CNN
F 0 "#PWR50" H 5550 4700 50 0001 C CNN
F 1 "VFPGA33" H 5568 5024 50 0000 C CNN
F 2 "" H 5550 4850 50 0000 C CNN
F 3 "" H 5550 4850 50 0000 C CNN
@ -1838,10 +1839,10 @@ F 3 "" H 5550 4850 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR23
L VFPGA33 #PWR39
U 1 1 56C69FA9
P 3700 4850
F 0 "#PWR23" H 3700 4700 50 0001 C CNN
F 0 "#PWR39" H 3700 4700 50 0001 C CNN
F 1 "VFPGA33" H 3718 5024 50 0000 C CNN
F 2 "" H 3700 4850 50 0000 C CNN
F 3 "" H 3700 4850 50 0000 C CNN
@ -1849,10 +1850,10 @@ F 3 "" H 3700 4850 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR42
L VFPGA33 #PWR58
U 1 1 56C6AF05
P 7900 4800
F 0 "#PWR42" H 7900 4650 50 0001 C CNN
F 0 "#PWR58" H 7900 4650 50 0001 C CNN
F 1 "VFPGA33" H 7918 4974 50 0000 C CNN
F 2 "" H 7900 4800 50 0000 C CNN
F 3 "" H 7900 4800 50 0000 C CNN
@ -1877,9 +1878,11 @@ Wire Wire Line
Connection ~ 3650 7200
Connection ~ 3650 6850
$Comp
L IS42S16800F U7
L IS42S16800F-RESCUE-fpgna U7
U 1 1 56C702B2
P 1100 6100
AR Path="/56C702B2" Ref="U7" Part="1"
AR Path="/563244F7/56C702B2" Ref="U7" Part="1"
F 0 "U7" H 1375 6287 60 0000 C CNN
F 1 "IS42S16800F" H 1375 6181 60 0000 C CNN
F 2 "smd:TSOP-54" H 1100 6100 60 0001 C CNN
@ -1898,10 +1901,10 @@ Wire Wire Line
900 6300 850 6300
Connection ~ 850 6300
$Comp
L VFPGA33 #PWR2
L VFPGA33 #PWR18
U 1 1 56C7605B
P 850 6000
F 0 "#PWR2" H 850 5850 50 0001 C CNN
F 0 "#PWR18" H 850 5850 50 0001 C CNN
F 1 "VFPGA33" H 868 6174 50 0000 C CNN
F 2 "" H 850 6000 50 0000 C CNN
F 3 "" H 850 6000 50 0000 C CNN
@ -1909,10 +1912,10 @@ F 3 "" H 850 6000 50 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR12
L VFPGA33 #PWR28
U 1 1 56C7613E
P 1900 6000
F 0 "#PWR12" H 1900 5850 50 0001 C CNN
F 0 "#PWR28" H 1900 5850 50 0001 C CNN
F 1 "VFPGA33" H 1918 6174 50 0000 C CNN
F 2 "" H 1900 6000 50 0000 C CNN
F 3 "" H 1900 6000 50 0000 C CNN
@ -1956,10 +1959,10 @@ Wire Wire Line
900 6650 850 6650
Connection ~ 850 6650
$Comp
L GNDD #PWR3
L GNDD #PWR19
U 1 1 56C779A7
P 850 7050
F 0 "#PWR3" H 850 6800 50 0001 C CNN
F 0 "#PWR19" H 850 6800 50 0001 C CNN
F 1 "GNDD" H 850 6900 50 0000 C CNN
F 2 "" H 850 7050 60 0000 C CNN
F 3 "" H 850 7050 60 0000 C CNN
@ -1967,10 +1970,10 @@ F 3 "" H 850 7050 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR13
L GNDD #PWR29
U 1 1 56C77AD2
P 1900 7050
F 0 "#PWR13" H 1900 6800 50 0001 C CNN
F 0 "#PWR29" H 1900 6800 50 0001 C CNN
F 1 "GNDD" H 1900 6900 50 0000 C CNN
F 2 "" H 1900 7050 60 0000 C CNN
F 3 "" H 1900 7050 60 0000 C CNN
@ -2022,10 +2025,10 @@ F 3 "" H 2850 6500 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L GNDD #PWR17
L GNDD #PWR33
U 1 1 56C7870C
P 2350 6750
F 0 "#PWR17" H 2350 6500 50 0001 C CNN
F 0 "#PWR33" H 2350 6500 50 0001 C CNN
F 1 "GNDD" H 2350 6600 50 0000 C CNN
F 2 "" H 2350 6750 60 0000 C CNN
F 3 "" H 2350 6750 60 0000 C CNN
@ -2041,10 +2044,10 @@ Wire Wire Line
Wire Wire Line
2350 6750 2350 6650
$Comp
L VFPGA33 #PWR16
L VFPGA33 #PWR32
U 1 1 56C78A86
P 2350 6250
F 0 "#PWR16" H 2350 6100 50 0001 C CNN
F 0 "#PWR32" H 2350 6100 50 0001 C CNN
F 1 "VFPGA33" H 2368 6424 50 0000 C CNN
F 2 "" H 2350 6250 50 0000 C CNN
F 3 "" H 2350 6250 50 0000 C CNN

487
sdram.sch
View File

@ -1,4 +1,5 @@
EESchema Schematic File Version 2
LIBS:fpgna-rescue
LIBS:power
LIBS:device
LIBS:transistors
@ -52,9 +53,11 @@ Comment3 ""
Comment4 ""
$EndDescr
$Comp
L IS42S16800F U7
L IS42S16800F-RESCUE-fpgna U7
U 2 1 56C6F7AD
P 3300 2600
AR Path="/56C6F7AD" Ref="U7" Part="2"
AR Path="/56C6F777/56C6F7AD" Ref="U7" Part="2"
F 0 "U7" H 3575 2787 60 0000 C CNN
F 1 "IS42S16800F" H 3575 2681 60 0000 C CNN
F 2 "smd:TSOP-54" H 3300 2600 60 0001 C CNN
@ -63,9 +66,11 @@ F 3 "" H 3300 2600 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L IS42S16800F U7
L IS42S16800F-RESCUE-fpgna U7
U 3 1 56C6F7EB
P 1300 2750
AR Path="/56C6F7EB" Ref="U7" Part="3"
AR Path="/56C6F777/56C6F7EB" Ref="U7" Part="3"
F 0 "U7" H 1575 2937 60 0000 C CNN
F 1 "IS42S16800F" H 1575 2831 60 0000 C CNN
F 2 "smd:TSOP-54" H 1300 2750 60 0001 C CNN
@ -74,9 +79,11 @@ F 3 "" H 1300 2750 60 0000 C CNN
1 0 0 -1
$EndComp
$Comp
L IS42S16800F U7
L IS42S16800F-RESCUE-fpgna U7
U 4 1 56C6F883
P 1300 3650
AR Path="/56C6F883" Ref="U7" Part="4"
AR Path="/56C6F777/56C6F883" Ref="U7" Part="4"
F 0 "U7" H 1878 3553 60 0000 L CNN
F 1 "IS42S16800F" H 1878 3447 60 0000 L CNN
F 2 "smd:TSOP-54" H 1300 3650 60 0001 C CNN
@ -165,16 +172,16 @@ NoConn ~ 1100 3850
$Comp
L LFXP2-5E-6TN144C U?
U 4 1 56C7D38D
P 9400 2400
P 9400 2300
AR Path="/56C43C85/56C7D38D" Ref="U?" Part="4"
AR Path="/56C6F777/56C7D38D" Ref="U3" Part="4"
F 0 "U3" H 9400 3337 60 0000 C CNN
F 1 "LFXP2-5E-6TN144C" H 9400 3231 60 0000 C CNN
F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 8700 2750 60 0001 C CNN
F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 8350 3650 60 0001 C CNN
F 4 "1.0" H 5750 3550 60 0001 C CNN "Version"
F 5 "Makise Kurisu <kurisu@shimatta.de>" H 6550 3450 60 0001 C CNN "Author"
4 9400 2400
F 0 "U3" H 9400 3237 60 0000 C CNN
F 1 "LFXP2-5E-6TN144C" H 9400 3131 60 0000 C CNN
F 2 "Housings_QFP:LQFP-144_20x20mm_Pitch0.5mm" H 8700 2650 60 0001 C CNN
F 3 "http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/LatticeXP2/LatticeXP2FamilyDataSheet.pdf" H 8350 3550 60 0001 C CNN
F 4 "1.0" H 5750 3450 60 0001 C CNN "Version"
F 5 "Makise Kurisu <kurisu@shimatta.de>" H 6550 3350 60 0001 C CNN "Author"
4 9400 2300
1 0 0 -1
$EndComp
$Comp
@ -304,42 +311,6 @@ Wire Wire Line
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Wire Wire Line
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Text Label 5850 1800 0 60 ~ 0
DQ15
Text Label 5850 1900 0 60 ~ 0
DQ0
Text Label 5850 2000 0 60 ~ 0
DQ14
Text Label 5850 2100 0 60 ~ 0
DQ1
Text Label 5850 2200 0 60 ~ 0
DQ13
Text Label 5850 2300 0 60 ~ 0
DQ2
Text Label 5850 2400 0 60 ~ 0
DQ12
Text Label 5850 2500 0 60 ~ 0
DQ3
Text Label 5850 2600 0 60 ~ 0
DQ11
Text Label 5850 2700 0 60 ~ 0
DQ4
Text Label 5850 2800 0 60 ~ 0
DQ10
Text Label 5850 2900 0 60 ~ 0
DQ5
Text Label 5850 3000 0 60 ~ 0
DQ9
Text Label 5850 3100 0 60 ~ 0
DQ6
Text Label 5850 3200 0 60 ~ 0
DQ8
Text Label 5850 3300 0 60 ~ 0
DQ7
Text Label 5850 3400 0 60 ~ 0
DQML
Text Label 5850 3500 0 60 ~ 0
DQMH
Wire Wire Line
7450 1800 7800 1800
Wire Wire Line
@ -356,87 +327,45 @@ Wire Wire Line
7450 2400 7800 2400
Wire Wire Line
7450 2500 7800 2500
Text Label 7800 1800 2 60 ~ 0
WE
Text Label 7800 1900 2 60 ~ 0
CLK
Text Label 7800 2000 2 60 ~ 0
CAS
Text Label 7800 2100 2 60 ~ 0
CKE
Text Label 7800 2200 2 60 ~ 0
RAS
Text Label 7800 2300 2 60 ~ 0
CS
Text Label 7800 2400 2 60 ~ 0
BA0
Text Label 7800 2500 2 60 ~ 0
BA1
Wire Wire Line
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Wire Wire Line
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10050 2400 10350 2400
Wire Wire Line
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10050 2200 10350 2200
Wire Wire Line
8750 2200 8500 2200
10050 2100 10350 2100
Wire Wire Line
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10050 2000 10350 2000
Wire Wire Line
8750 2400 8500 2400
10050 1900 10350 1900
Wire Wire Line
8750 2500 8500 2500
Wire Wire Line
8750 2600 8500 2600
Wire Wire Line
8750 2700 8500 2700
Wire Wire Line
8750 2800 8500 2800
Wire Wire Line
8750 2900 8500 2900
Wire Wire Line
8750 3000 8500 3000
Wire Wire Line
8750 3100 8500 3100
Wire Wire Line
8750 3200 8500 3200
Wire Wire Line
8750 3300 8500 3300
Wire Wire Line
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10050 1800 10350 1800
Wire Wire Line
8750 3500 8500 3500
Wire Wire Line
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Text Label 8500 1900 0 60 ~ 0
A11
Text Label 8500 2000 0 60 ~ 0
A9
Text Label 8500 2100 0 60 ~ 0
A8
Text Label 8500 2200 0 60 ~ 0
A10
Text Label 8500 2300 0 60 ~ 0
A7
Text Label 8500 2400 0 60 ~ 0
A0
Text Label 8500 2500 0 60 ~ 0
A6
Text Label 8500 2600 0 60 ~ 0
A1
Text Label 8500 2700 0 60 ~ 0
A5
Text Label 8500 2800 0 60 ~ 0
A2
Text Label 8500 2900 0 60 ~ 0
A4
Text Label 8500 3000 0 60 ~ 0
A3
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
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Wire Wire Line
8750 2800 8500 2800
Wire Wire Line
8750 2700 8500 2700
Wire Wire Line
8750 2600 8500 2600
$Comp
L C C?
L C C51
U 1 1 56C80517
P 5750 4100
F 0 "C?" H 5800 4200 50 0000 L CNN
F 0 "C51" H 5800 4200 50 0000 L CNN
F 1 "100n" H 5800 4000 50 0000 L CNN
F 2 "" H 5788 3950 50 0001 C CNN
F 3 "" H 5750 4100 50 0000 C CNN
@ -444,10 +373,10 @@ F 3 "" H 5750 4100 50 0000 C CNN
-1 0 0 -1
$EndComp
$Comp
L C C?
L C C50
U 1 1 56C8051E
P 5550 4100
F 0 "C?" H 5600 4200 50 0000 L CNN
F 0 "C50" H 5600 4200 50 0000 L CNN
F 1 "100n" H 5600 4000 50 0000 L CNN
F 2 "" H 5588 3950 50 0001 C CNN
F 3 "" H 5550 4100 50 0000 C CNN
@ -455,10 +384,10 @@ F 3 "" H 5550 4100 50 0000 C CNN
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR5
U 1 1 56C80525
P 6100 4400
F 0 "#PWR?" H 6100 4150 50 0001 C CNN
F 0 "#PWR5" H 6100 4150 50 0001 C CNN
F 1 "GND" H 6108 4226 50 0000 C CNN
F 2 "" H 6100 4400 50 0000 C CNN
F 3 "" H 6100 4400 50 0000 C CNN
@ -466,10 +395,10 @@ F 3 "" H 6100 4400 50 0000 C CNN
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR4
U 1 1 56C8052B
P 5900 4400
F 0 "#PWR?" H 5900 4150 50 0001 C CNN
F 0 "#PWR4" H 5900 4150 50 0001 C CNN
F 1 "GND" H 5908 4226 50 0000 C CNN
F 2 "" H 5900 4400 50 0000 C CNN
F 3 "" H 5900 4400 50 0000 C CNN
@ -477,10 +406,10 @@ F 3 "" H 5900 4400 50 0000 C CNN
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR2
U 1 1 56C80531
P 5650 4400
F 0 "#PWR?" H 5650 4150 50 0001 C CNN
F 0 "#PWR2" H 5650 4150 50 0001 C CNN
F 1 "GND" H 5658 4226 50 0000 C CNN
F 2 "" H 5650 4400 50 0000 C CNN
F 3 "" H 5650 4400 50 0000 C CNN
@ -499,10 +428,10 @@ Wire Wire Line
5650 4400 5650 4250
Connection ~ 5650 4250
$Comp
L VFPGA33 #PWR?
L VFPGA33 #PWR1
U 1 1 56C8053D
P 5550 3850
F 0 "#PWR?" H 5550 3700 50 0001 C CNN
F 0 "#PWR1" H 5550 3700 50 0001 C CNN
F 1 "VFPGA33" H 5568 4024 50 0000 C CNN
F 2 "" H 5550 3850 50 0000 C CNN
F 3 "" H 5550 3850 50 0000 C CNN
@ -510,10 +439,10 @@ F 3 "" H 5550 3850 50 0000 C CNN
-1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR?
L VFPGA33 #PWR3
U 1 1 56C80543
P 5750 3750
F 0 "#PWR?" H 5750 3600 50 0001 C CNN
F 0 "#PWR3" H 5750 3600 50 0001 C CNN
F 1 "VFPGA33" H 5768 3924 50 0000 C CNN
F 2 "" H 5750 3750 50 0000 C CNN
F 3 "" H 5750 3750 50 0000 C CNN
@ -524,7 +453,7 @@ Wire Wire Line
5550 3850 5550 3950
Connection ~ 5550 3900
Wire Wire Line
5750 4250 5550 4250
5550 4250 5750 4250
Wire Wire Line
5750 3750 5750 3950
Wire Wire Line
@ -533,110 +462,110 @@ Wire Wire Line
6150 3800 5750 3800
Connection ~ 5750 3800
$Comp
L C C?
L C C54
U 1 1 56C80792
P 8350 4200
F 0 "C?" H 8400 4300 50 0000 L CNN
F 1 "100n" H 8400 4100 50 0000 L CNN
F 2 "" H 8388 4050 50 0001 C CNN
F 3 "" H 8350 4200 50 0000 C CNN
1 8350 4200
P 8350 4100
F 0 "C54" H 8400 4200 50 0000 L CNN
F 1 "100n" H 8400 4000 50 0000 L CNN
F 2 "" H 8388 3950 50 0001 C CNN
F 3 "" H 8350 4100 50 0000 C CNN
1 8350 4100
-1 0 0 -1
$EndComp
$Comp
L C C?
L C C53
U 1 1 56C80798
P 8150 4200
F 0 "C?" H 8200 4300 50 0000 L CNN
F 1 "100n" H 8200 4100 50 0000 L CNN
F 2 "" H 8188 4050 50 0001 C CNN
F 3 "" H 8150 4200 50 0000 C CNN
1 8150 4200
P 8150 4100
F 0 "C53" H 8200 4200 50 0000 L CNN
F 1 "100n" H 8200 4000 50 0000 L CNN
F 2 "" H 8188 3950 50 0001 C CNN
F 3 "" H 8150 4100 50 0000 C CNN
1 8150 4100
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR13
U 1 1 56C8079E
P 8700 4500
F 0 "#PWR?" H 8700 4250 50 0001 C CNN
F 1 "GND" H 8708 4326 50 0000 C CNN
F 2 "" H 8700 4500 50 0000 C CNN
F 3 "" H 8700 4500 50 0000 C CNN
1 8700 4500
P 8700 4400
F 0 "#PWR13" H 8700 4150 50 0001 C CNN
F 1 "GND" H 8708 4226 50 0000 C CNN
F 2 "" H 8700 4400 50 0000 C CNN
F 3 "" H 8700 4400 50 0000 C CNN
1 8700 4400
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR12
U 1 1 56C807A4
P 8500 4500
F 0 "#PWR?" H 8500 4250 50 0001 C CNN
F 1 "GND" H 8508 4326 50 0000 C CNN
F 2 "" H 8500 4500 50 0000 C CNN
F 3 "" H 8500 4500 50 0000 C CNN
1 8500 4500
P 8500 4400
F 0 "#PWR12" H 8500 4150 50 0001 C CNN
F 1 "GND" H 8508 4226 50 0000 C CNN
F 2 "" H 8500 4400 50 0000 C CNN
F 3 "" H 8500 4400 50 0000 C CNN
1 8500 4400
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR10
U 1 1 56C807AA
P 8250 4500
F 0 "#PWR?" H 8250 4250 50 0001 C CNN
F 1 "GND" H 8258 4326 50 0000 C CNN
F 2 "" H 8250 4500 50 0000 C CNN
F 3 "" H 8250 4500 50 0000 C CNN
1 8250 4500
P 8250 4400
F 0 "#PWR10" H 8250 4150 50 0001 C CNN
F 1 "GND" H 8258 4226 50 0000 C CNN
F 2 "" H 8250 4400 50 0000 C CNN
F 3 "" H 8250 4400 50 0000 C CNN
1 8250 4400
-1 0 0 -1
$EndComp
Wire Wire Line
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8700 4400 8700 4100
Wire Wire Line
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8700 4100 8750 4100
Wire Wire Line
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8750 4000 8500 4000
Wire Wire Line
8500 4100 8500 4500
8500 4000 8500 4400
Wire Wire Line
8250 4500 8250 4350
Connection ~ 8250 4350
8250 4400 8250 4250
Connection ~ 8250 4250
$Comp
L VFPGA33 #PWR?
L VFPGA33 #PWR9
U 1 1 56C807B6
P 8150 3950
F 0 "#PWR?" H 8150 3800 50 0001 C CNN
F 1 "VFPGA33" H 8168 4124 50 0000 C CNN
F 2 "" H 8150 3950 50 0000 C CNN
F 3 "" H 8150 3950 50 0000 C CNN
1 8150 3950
P 8150 3850
F 0 "#PWR9" H 8150 3700 50 0001 C CNN
F 1 "VFPGA33" H 8168 4024 50 0000 C CNN
F 2 "" H 8150 3850 50 0000 C CNN
F 3 "" H 8150 3850 50 0000 C CNN
1 8150 3850
-1 0 0 -1
$EndComp
$Comp
L VFPGA33 #PWR?
L VFPGA33 #PWR11
U 1 1 56C807BC
P 8350 3850
F 0 "#PWR?" H 8350 3700 50 0001 C CNN
F 1 "VFPGA33" H 8368 4024 50 0000 C CNN
F 2 "" H 8350 3850 50 0000 C CNN
F 3 "" H 8350 3850 50 0000 C CNN
1 8350 3850
P 8350 3750
F 0 "#PWR11" H 8350 3600 50 0001 C CNN
F 1 "VFPGA33" H 8368 3924 50 0000 C CNN
F 2 "" H 8350 3750 50 0000 C CNN
F 3 "" H 8350 3750 50 0000 C CNN
1 8350 3750
-1 0 0 -1
$EndComp
Wire Wire Line
8150 3950 8150 4050
Connection ~ 8150 4000
8150 3850 8150 3950
Connection ~ 8150 3900
Wire Wire Line
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8150 4250 8350 4250
Wire Wire Line
8350 3850 8350 4050
8350 3750 8350 3950
Wire Wire Line
8150 4000 8750 4000
8150 3900 8750 3900
Wire Wire Line
8750 3900 8350 3900
Connection ~ 8350 3900
8750 3800 8350 3800
Connection ~ 8350 3800
$Comp
L C C?
L C C52
U 1 1 56C80907
P 7700 4200
F 0 "C?" H 7750 4300 50 0000 L CNN
F 0 "C52" H 7750 4300 50 0000 L CNN
F 1 "100n" H 7750 4100 50 0000 L CNN
F 2 "" H 7738 4050 50 0001 C CNN
F 3 "" H 7700 4200 50 0000 C CNN
@ -644,10 +573,10 @@ F 3 "" H 7700 4200 50 0000 C CNN
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR6
U 1 1 56C8090E
P 7500 4400
F 0 "#PWR?" H 7500 4150 50 0001 C CNN
F 0 "#PWR6" H 7500 4150 50 0001 C CNN
F 1 "GND" H 7508 4226 50 0000 C CNN
F 2 "" H 7500 4400 50 0000 C CNN
F 3 "" H 7500 4400 50 0000 C CNN
@ -655,10 +584,10 @@ F 3 "" H 7500 4400 50 0000 C CNN
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR8
U 1 1 56C80914
P 7700 4400
F 0 "#PWR?" H 7700 4150 50 0001 C CNN
F 0 "#PWR8" H 7700 4150 50 0001 C CNN
F 1 "GND" H 7708 4226 50 0000 C CNN
F 2 "" H 7700 4400 50 0000 C CNN
F 3 "" H 7700 4400 50 0000 C CNN
@ -676,10 +605,10 @@ Wire Wire Line
Wire Wire Line
7700 4400 7700 4350
$Comp
L VFPGA33 #PWR?
L VFPGA33 #PWR7
U 1 1 56C8091F
P 7700 3750
F 0 "#PWR?" H 7700 3600 50 0001 C CNN
F 0 "#PWR7" H 7700 3600 50 0001 C CNN
F 1 "VFPGA33" H 7718 3924 50 0000 C CNN
F 2 "" H 7700 3750 50 0000 C CNN
F 3 "" H 7700 3750 50 0000 C CNN
@ -688,58 +617,152 @@ F 3 "" H 7700 3750 50 0000 C CNN
$EndComp
Connection ~ 7700 4000
$Comp
L C C?
L C C55
U 1 1 56C80AD2
P 10300 4300
F 0 "C?" H 10350 4400 50 0000 L CNN
F 1 "100n" H 10350 4200 50 0000 L CNN
F 2 "" H 10338 4150 50 0001 C CNN
F 3 "" H 10300 4300 50 0000 C CNN
1 10300 4300
P 10300 4200
F 0 "C55" H 10350 4300 50 0000 L CNN
F 1 "100n" H 10350 4100 50 0000 L CNN
F 2 "" H 10338 4050 50 0001 C CNN
F 3 "" H 10300 4200 50 0000 C CNN
1 10300 4200
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR14
U 1 1 56C80AD8
P 10100 4500
F 0 "#PWR?" H 10100 4250 50 0001 C CNN
F 1 "GND" H 10108 4326 50 0000 C CNN
F 2 "" H 10100 4500 50 0000 C CNN
F 3 "" H 10100 4500 50 0000 C CNN
1 10100 4500
P 10100 4400
F 0 "#PWR14" H 10100 4150 50 0001 C CNN
F 1 "GND" H 10108 4226 50 0000 C CNN
F 2 "" H 10100 4400 50 0000 C CNN
F 3 "" H 10100 4400 50 0000 C CNN
1 10100 4400
-1 0 0 -1
$EndComp
$Comp
L GND #PWR?
L GND #PWR16
U 1 1 56C80ADE
P 10300 4500
F 0 "#PWR?" H 10300 4250 50 0001 C CNN
F 1 "GND" H 10308 4326 50 0000 C CNN
F 2 "" H 10300 4500 50 0000 C CNN
F 3 "" H 10300 4500 50 0000 C CNN
1 10300 4500
P 10300 4400
F 0 "#PWR16" H 10300 4150 50 0001 C CNN
F 1 "GND" H 10308 4226 50 0000 C CNN
F 2 "" H 10300 4400 50 0000 C CNN
F 3 "" H 10300 4400 50 0000 C CNN
1 10300 4400
-1 0 0 -1
$EndComp
Wire Wire Line
10300 3850 10300 4150
10300 3750 10300 4050
Wire Wire Line
10300 4100 10050 4100
10300 4000 10050 4000
Wire Wire Line
10100 4500 10100 4200
10100 4400 10100 4100
Wire Wire Line
10100 4200 10050 4200
10100 4100 10050 4100
Wire Wire Line
10300 4500 10300 4450
10300 4400 10300 4350
$Comp
L VFPGA33 #PWR?
L VFPGA33 #PWR15
U 1 1 56C80AE9
P 10300 3850
F 0 "#PWR?" H 10300 3700 50 0001 C CNN
F 1 "VFPGA33" H 10318 4024 50 0000 C CNN
F 2 "" H 10300 3850 50 0000 C CNN
F 3 "" H 10300 3850 50 0000 C CNN
1 10300 3850
P 10300 3750
F 0 "#PWR15" H 10300 3600 50 0001 C CNN
F 1 "VFPGA33" H 10318 3924 50 0000 C CNN
F 2 "" H 10300 3750 50 0000 C CNN
F 3 "" H 10300 3750 50 0000 C CNN
1 10300 3750
-1 0 0 -1
$EndComp
Connection ~ 10300 4100
Connection ~ 10300 4000
Wire Wire Line
10050 2300 10350 2300
Text Label 10350 2500 2 60 ~ 0
DQ15
Text Label 10350 2400 2 60 ~ 0
DQ0
Text Label 10350 2300 2 60 ~ 0
DQ14
Text Label 10350 2200 2 60 ~ 0
DQ1
Text Label 10350 2100 2 60 ~ 0
DQ13
Text Label 10350 2000 2 60 ~ 0
DQ2
Text Label 10350 1900 2 60 ~ 0
DQ12
Text Label 10350 1800 2 60 ~ 0
DQ3
Text Label 8500 3500 0 60 ~ 0
DQ11
Text Label 8500 3400 0 60 ~ 0
DQ4
Text Label 8500 3300 0 60 ~ 0
DQ10
Text Label 8500 3200 0 60 ~ 0
DQ5
Text Label 8500 3100 0 60 ~ 0
DQ9
Text Label 8500 3000 0 60 ~ 0
DQ6
Text Label 8500 2900 0 60 ~ 0
DQ8
Text Label 8500 2800 0 60 ~ 0
DQ7
Text Label 8500 2700 0 60 ~ 0
DQML
Text Label 8500 2600 0 60 ~ 0
DQMH
Wire Wire Line
8750 2500 8500 2500
Wire Wire Line
8750 2400 8500 2400
Wire Wire Line
8750 2300 8500 2300
Wire Wire Line
8750 2200 8500 2200
Wire Wire Line
8750 2100 8500 2100
Wire Wire Line
8750 2000 8500 2000
Wire Wire Line
8750 1900 8500 1900
Wire Wire Line
8750 1800 8500 1800
Text Label 8500 2500 0 60 ~ 0
WE
Text Label 8500 2400 0 60 ~ 0
CLK
Text Label 8500 2300 0 60 ~ 0
CAS
Text Label 8500 2200 0 60 ~ 0
CKE
Text Label 8500 2100 0 60 ~ 0
RAS
Text Label 8500 2000 0 60 ~ 0
CS
Text Label 8500 1900 0 60 ~ 0
BA0
Text Label 8500 1800 0 60 ~ 0
BA1
Text Label 7800 2500 2 60 ~ 0
A0
Text Label 7800 2400 2 60 ~ 0
A10
Text Label 7800 2300 2 60 ~ 0
A1
Text Label 7800 2200 2 60 ~ 0
A2
Text Label 7800 2100 2 60 ~ 0
A3
Text Label 7800 2000 2 60 ~ 0
A11
Text Label 7800 1900 2 60 ~ 0
A9
Text Label 7800 1800 2 60 ~ 0
A8
Text Label 5850 3500 0 60 ~ 0
A7
Text Label 5850 3400 0 60 ~ 0
A6
Text Label 5850 3200 0 60 ~ 0
A4
Text Label 5850 3300 0 60 ~ 0
A5
$EndSCHEMATC