52 lines
2.0 KiB
VHDL
52 lines
2.0 KiB
VHDL
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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package wishbone_pkg is
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constant WISHBONE_ADDRESS_WIDTH : integer := 32;
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constant WISHBONE_DATA_WIDTH : integer := 32;
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subtype wishbone_address is std_logic_vector(WISHBONE_ADDRESS_WIDTH - 1 downto 0);
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subtype wishbone_data is std_logic_vector(WISHBONE_DATA_WIDTH - 1 downto 0);
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subtype wishbone_byte_select is std_logic_vector((WISHBONE_ADDRESS_WIDTH / 8) - 1 downto 0);
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subtype wishbone_cycle_type is std_logic_vector(2 downto 0);
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subtype wishbone_burst_type is std_logic_vector(1 downto 0);
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type wishbone_master_out is record
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cyc : std_logic;
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stb : std_logic;
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adr : wishbone_address;
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sel : wishbone_byte_select;
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we : std_logic;
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dat : wishbone_data;
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end record wishbone_master_out;
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subtype wishbone_slave_in is wishbone_master_out;
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type wishbone_slave_out is record
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ack : std_logic;
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err : std_logic;
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rty : std_logic;
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stall : std_logic;
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dat : wishbone_data;
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end record wishbone_slave_out;
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subtype wishbone_master_in is wishbone_slave_out;
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type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
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type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;
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subtype wishbone_slave_in_vector is wishbone_master_out_vector;
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subtype wishbone_master_in_vector is wishbone_slave_out_vector;
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type wishbone_address_vector is array (natural range <>) of wishbone_address;
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type wishbone_data_vector is array (natural range <>) of wishbone_data;
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end wishbone_pkg;
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