29 lines
823 B
Bash
29 lines
823 B
Bash
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#!/bin/bash
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mkdir -p build
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cd build
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set -e
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../run.py --compile
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BASEDIR=".."
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DEVICE=--u4k # --up5k, --u4k
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PACKAGE=sg48
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# Collect pre-analyzed VHDL sources
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GHDLINCDIRS=`find ./vunit_out/ghdl/libraries -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '`
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# Collect Verilog sources
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SERV="$BASEDIR/hdl/serv"
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VLOGS=`echo ../hdl/serv/rtl/*.v`
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VLOGS="$VLOGS $SERV/servant/servant_ram.v $SERV/servant/servant_timer.v"
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# Synthesize and PnR
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# -device <hx | lp | u>
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yosys -m ghdl -p "read_verilog $VLOGS; ghdl --std=08 $GHDLINCDIRS design.top; synth_ice40 -abc9 -device u -top top -json netlist.json"
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nextpnr-ice40 $DEVICE --package $PACKAGE --freq 12 --asc netlist.asc --report report.json --detailed-timing-report --json netlist.json --pcf ../constraints.pcf
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# Generate bitstream
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icepack netlist.asc bitstream.bin
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