trashernet-soc/fpga/build.sh

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#!/bin/bash
mkdir -p build
cd build
set -e
../run.py --compile
BASEDIR=".."
DEVICE=--u4k # --up5k, --u4k
PACKAGE=sg48
# Collect pre-analyzed VHDL sources
GHDLINCDIRS=`find ./vunit_out/ghdl/libraries -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '`
# Collect Verilog sources
SERV="$BASEDIR/hdl/serv"
VLOGS=`echo ../hdl/serv/rtl/*.v`
VLOGS="$VLOGS $SERV/servant/servant_ram.v $SERV/servant/servant_timer.v"
# Synthesize and PnR
# -device <hx | lp | u>
yosys -m ghdl -p "read_verilog $VLOGS; ghdl --std=08 $GHDLINCDIRS design.top; synth_ice40 -abc9 -device u -top top -json netlist.json"
nextpnr-ice40 $DEVICE --package $PACKAGE --freq 12 --asc netlist.asc --report report.json --detailed-timing-report --json netlist.json --pcf ../constraints.pcf
# Generate bitstream
icepack netlist.asc bitstream.bin