trashernet-soc/fpga/hdl/design/pll0.vhd

-- -------------------------------------------------------------------------- --
--              TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs              --
-- -------------------------------------------------------------------------- --
-- TODO
-- -------------------------------------------------------------------------- --
-- Author       : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License      : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --

library IEEE;
use IEEE.std_logic_1164.all;

library generics;
use generics.ice40_components.all;

entity pll0 is
	generic(
		F_CLK     : in integer;
		F_CLK_PHY : in integer
	);
	port(
		clk_in      : in  std_logic;
		clk_out     : out std_logic;
		clk_out_phy : out std_logic;
		locked      : out std_logic
	);
end pll0;

architecture Structure of pll0 is
	signal clk_int_osc : std_logic;
begin
	SB_HFOSC_inst : component SB_HFOSC
		generic map(
			CLKHF_DIV => "0b01"         -- 24 MHz
		)
		port map(
			CLKHFPU => '1',
			CLKHFEN => '1',
			CLKHF   => clk_int_osc
		);

	--	SB_PLL40_PAD_inst : component SB_PLL40_PAD
	--		generic map(
	--			FEEDBACK_PATH => "SIMPLE",
	--			DIVR          => "0000",
	--			DIVF          => "1000010",
	--			DIVQ          => "100",
	--			FILTER_RANGE  => "001"
	--		)
	--		port map(
	--			RESETB     => '1',
	--			BYPASS     => '0',
	--			PACKAGEPIN => clk_in,
	--			PLLOUTCORE => clk_out_phy
	--		);

	clk_out_phy <= clk_in;

	-- Not clean, but it works...
	ckdiv2 : process(clk_out_phy) is
	begin
		if rising_edge(clk_out_phy) then
			clk_out <= not clk_out;
		end if;
	end process ckdiv2;

	assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure;
	assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure;
end Structure;