107 lines
3.3 KiB
VHDL
107 lines
3.3 KiB
VHDL
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity fifo is
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generic(
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SIZE : integer := 15 -- Entries in the FIFO (of size data), SIZE=(n^2)-1 recommended
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);
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port(
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-- generic ports
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clk : in std_logic; -- System clock
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rst_a : in std_logic; -- Asynchronous reset
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clr : in std_logic; -- Remove all entries
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-- FIFO in
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data_in : in std_logic_vector; -- Data input into FIFO
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write : in std_logic; -- Data is latched when `data_in_valid and not full`
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full : out std_logic; -- FIFO is full
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-- FIFO out
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data_out : out std_logic_vector; -- Data output from FIFO
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empty : out std_logic; -- FIFO is empty. '0' means "data is available".
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read : in std_logic; -- Acknowledge that `data_out` was read. The word is removed and next one shifted from FIFO when `read and not empty`.
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-- FIFO meta
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usage : out integer range 0 to SIZE -- Usage counter
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);
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end fifo;
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architecture rtl of fifo is
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constant MEMORY_WIDTH : integer := data_in'length;
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subtype pointer_t is integer range 0 to SIZE - 1;
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type memory_t is array (pointer_t) of std_logic_vector(MEMORY_WIDTH - 1 downto 0);
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signal memory : memory_t;
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signal read_pointer : pointer_t;
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signal write_pointer : pointer_t;
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signal read_pointer_last : pointer_t;
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begin
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fifo_p : process(rst_a, clk) is
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variable succesful_read : std_logic;
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variable succesful_write : std_logic;
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variable write_pointer_next : pointer_t;
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variable read_pointer_next : pointer_t;
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begin
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if rst_a then
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read_pointer <= 0;
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write_pointer <= 0;
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read_pointer_last <= SIZE - 1;
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usage <= 0;
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elsif rising_edge(clk) then
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succesful_read := read and not empty;
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succesful_write := write and (not full or succesful_read);
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write_pointer_next := write_pointer;
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read_pointer_next := read_pointer;
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if succesful_read then
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read_pointer_next := (read_pointer_next + 1) mod SIZE;
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read_pointer_last <= read_pointer;
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end if;
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if succesful_write then
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memory(write_pointer) <= data_in;
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write_pointer_next := (write_pointer_next + 1) mod SIZE;
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end if;
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if succesful_write xor succesful_read then
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if succesful_write then
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usage <= usage + 1;
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else
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usage <= usage - 1;
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end if;
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end if;
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read_pointer <= read_pointer_next;
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write_pointer <= write_pointer_next;
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if clr then
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read_pointer <= 0;
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write_pointer <= 0;
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read_pointer_last <= SIZE - 1;
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usage <= 0;
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end if;
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end if;
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end process fifo_p;
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full <= '1' when read_pointer_last = write_pointer else '0';
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empty <= '1' when (read_pointer = write_pointer) else '0';
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data_out <= memory(read_pointer);
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end rtl;
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