fpga: top: Refactor indentation

2024-11-08 15:52:46 +01:00 · 2024-11-08 15:52:46 +01:00 · 9487f5c2ef
commit 9487f5c2ef
parent f21122c54b
1 changed files with 4 additions and 4 deletions
--- a/fpga/hdl/design/top.vhd
+++ b/fpga/hdl/design/top.vhd
@ -237,10 +237,10 @@ begin

 	servant_rom_vhdl_inst : entity work.servant_ram_vhdl
 		generic map(
-			memfile   => "../sw/bootrom/bootrom.vhex",
-			read_only => true,
-			adr_width => 9,
-			force_vlog  => not in_simulation -- GHDL + Yosys doesn't keep the memfile
+			memfile    => "../sw/bootrom/bootrom.vhex",
+			read_only  => true,
+			adr_width  => 9,
+			force_vlog => not in_simulation -- GHDL + Yosys doesn't keep the memfile
 		)
 		port map(
 			clk  => clk,