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fpga: Add script to remove $asserts from netlists

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For some reason, GHDL adds some (not all) asserts to the
synthesis netlist. This script removes them.
This commit is contained in:
Markus Koch 2024-11-08 15:37:15 +01:00
parent 0943656548
commit f21122c54b
2 changed files with 15 additions and 0 deletions
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1
fpga/Makefile
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@ -46,6 +46,7 @@ $(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
# Collect GHDL sources from VUnit
$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
./patch_asserts.sh $@
$(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)

14
fpga/patch_asserts.sh Executable file
View File

@ -0,0 +1,14 @@
#!/bin/bash
file="$1"
echo "Removing \$assert from $file..."
LOCS=`grep -n '$assert' "$file" | sed 's/:.*//g'`
IFS=$'\n'
for LOC in $LOCS; do
START=$(($LOC-2))
END=$(($LOC+14))
echo "Deleting lines $START -> $END"
sed -i -e "${START},${END}d" "$file"
done