electronics/trashernet-soc
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
PCB, FPGA, and SW design to implement a tiny Ethernet-connected SoC based on SERV + Trashernet
37 Commits 2 Branches 1 Tag 1 MiB
Text 100%
f21122c54b
Go to file
Markus Koch f21122c54b fpga: Add script to remove $asserts from netlists 
For some reason, GHDL adds some (not all) asserts to the
synthesis netlist. This script removes them.
2024-11-08 15:37:15 +01:00
fpga fpga: Add script to remove $asserts from netlists 2024-11-08 15:37:15 +01:00
kicad Swap RX+ and - 2024-06-02 10:15:13 +02:00
sw/bootrom sw: bootrom: Improve performance and reduce size 2024-08-07 18:01:22 +02:00
tools tools: Update flasher script to new bus layout 2024-08-09 14:03:00 +02:00
.gitmodules fpga: Add NEORV32 as alternative CPU core 2024-09-27 14:44:28 +02:00
LICENSE-CC-BY-SA-4.0.TXT Add licensing information 2024-06-02 10:30:26 +02:00
LICENSE-MPL-2.0.txt doc: Add a copy of the MPL-2.0 2024-07-06 19:06:39 +02:00
README.MD fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00

README.MD

Trashernet SoC

PCB, FPGA, and SW design to implement a tiny Ethernet-connected SoC based on SERV + Trashernet.

License

Trashernet SoC, Copyright (C) 2024 Markus Koch markus@notsyncing.net

Hardware

The PCB design in /kicad is released under a Creative Commons Attribution-ShareAlike 4.0 International license.

You can find a copy of the full license in LICENSE-CC-BY-SA-4.0.TXT.

FPGA

The FPGA Source Code Form in /fpga is subject to the terms of the Mozilla Public License, v. 2.0.

You can find a copy of the full license in LICENSE-MPL-2.0.txt.

Note that this design incorporates code from third-party projects, which may come with further restrictions. For details, refer to the individual projects's licensing terms:

SW

TBD.