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fpga: top: Refactor indentation

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This commit is contained in:
Markus Koch 2024-11-08 15:52:46 +01:00
parent f21122c54b
commit 9487f5c2ef
1 changed files with 4 additions and 4 deletions
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8
fpga/hdl/design/top.vhd
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@ -237,10 +237,10 @@ begin
servant_rom_vhdl_inst : entity work.servant_ram_vhdl servant_rom_vhdl_inst : entity work.servant_ram_vhdl
generic map( generic map(
memfile => "../sw/bootrom/bootrom.vhex", memfile => "../sw/bootrom/bootrom.vhex",
read_only => true, read_only => true,
adr_width => 9, adr_width => 9,
force_vlog => not in_simulation -- GHDL + Yosys doesn't keep the memfile force_vlog => not in_simulation -- GHDL + Yosys doesn't keep the memfile
) )
port map( port map(
clk => clk, clk => clk,