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fpga: Update UART baud rate to 250 kbaud/s

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This commit is contained in:
Markus Koch 2024-08-09 11:31:59 +02:00
parent 876693ca5f
commit b06ccdda2a
2 changed files with 2 additions and 2 deletions
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2
fpga/hdl/design/top.vhd
View File

@ -22,7 +22,7 @@ entity top is
-- System configuration -- System configuration
F_CLK : integer := 25000000; F_CLK : integer := 25000000;
F_CLK_PHY : integer := 50000000; F_CLK_PHY : integer := 50000000;
UART_BAUD : integer := 19200 UART_BAUD : integer := 250000
); );
port( port(
clk_50m : in std_logic; -- System clock clk_50m : in std_logic; -- System clock

2
tools/flash.py
View File

@ -17,7 +17,7 @@ from ast import literal_eval
def eprint(*args, **kwargs): def eprint(*args, **kwargs):
print(*args, file=sys.stderr, **kwargs) print(*args, file=sys.stderr, **kwargs)
ser = serial.Serial('/dev/ttyUSB0', 19200, timeout=2) ser = serial.Serial('/dev/ttyUSB0', 250000, timeout=2)
def sread(address, length, quiet = False): def sread(address, length, quiet = False):
if not quiet: if not quiet: