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9487f5c2ef
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fpga: top: Refactor indentation
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2024-11-08 15:52:46 +01:00 |
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cc4b088173
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fpga: ram: Use Verilog model for synthesis and VHDL for simulation
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2024-09-27 16:34:55 +02:00 |
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7497f1f6bb
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fpga: Add Sigasi / Code project
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2024-09-27 14:47:45 +02:00 |
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ba299e537b
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fpga: Add NEORV32 as alternative CPU core
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2024-09-27 14:44:28 +02:00 |
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e7d9f391ef
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fpga: Clean up clocking code
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2024-08-09 14:01:16 +02:00 |
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b06ccdda2a
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fpga: Update UART baud rate to 250 kbaud/s
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2024-08-09 11:31:59 +02:00 |
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74280fb79a
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fpga: Implement single-instruction prefetching from external RAM
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2024-08-01 21:06:14 +02:00 |
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e81166a82c
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fpga: Implement functional Ethernet controller
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2024-07-23 19:13:42 +02:00 |
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dd7cf08b6f
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fpga: Continue work on full HW support
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2024-07-06 19:14:39 +02:00 |
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b7c1286d76
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fpga: Implement basic SERV SoC
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2024-06-22 11:28:15 +02:00 |
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