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49ccbea9e9
trashernet-soc
/
fpga
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Markus Koch
49ccbea9e9
fpga: aps6404l device model: Remove unnecessary newlines
2024-08-01 21:11:47 +02:00
..
hdl
fpga: aps6404l device model: Remove unnecessary newlines
2024-08-01 21:11:47 +02:00
.gitignore
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
constraints.pcf
fpga: Implement functional Ethernet controller
2024-07-23 19:13:42 +02:00
Makefile
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
run_physical.py
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
run.py
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00