trashernet-soc/fpga
2024-08-01 21:11:47 +02:00
..
hdl fpga: aps6404l device model: Remove unnecessary newlines 2024-08-01 21:11:47 +02:00
.gitignore fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
constraints.pcf fpga: Implement functional Ethernet controller 2024-07-23 19:13:42 +02:00
Makefile fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
run_physical.py fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
run.py fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00