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49ccbea9e9
trashernet-soc
/
fpga
/
hdl
History
Markus Koch
49ccbea9e9
fpga: aps6404l device model: Remove unnecessary newlines
2024-08-01 21:11:47 +02:00
..
bench
fpga: Implement single-instruction prefetching from external RAM
2024-08-01 21:06:14 +02:00
design
fpga: trashernet_phy_wb: Ensure LEDs blink even with constant traffic
2024-08-01 21:10:53 +02:00
device_models
fpga: aps6404l device model: Remove unnecessary newlines
2024-08-01 21:11:47 +02:00
generics
fpga: Add generic FIFO core
2024-07-26 10:55:32 +02:00
serv
@
086090046c
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00
trashernet
@
206332f3d1
fpga: Implement functional Ethernet controller
2024-07-23 19:13:42 +02:00
header.sh
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00