58 lines
1.7 KiB
VHDL
58 lines
1.7 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library IEEE;
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use IEEE.std_logic_1164.all;
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library generics;
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use generics.ice40_components.all;
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entity pll0 is
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generic(
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F_IN : in integer;
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F_CLK : in integer;
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F_CLK_PHY : in integer
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);
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port(
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clk_in : in std_logic;
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clk_out : out std_logic;
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clk_out_phy : out std_logic;
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locked : out std_logic
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);
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end pll0;
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architecture Structure of pll0 is
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signal clk_out_i : std_logic;
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begin
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-- Not clean, but it works...
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ckdiv2 : process(clk_out_phy) is
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begin
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if rising_edge(clk_out_phy) then
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clk_out_i <= not clk_out_i;
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end if;
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end process ckdiv2;
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SB_GB_inst : component SB_GB
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port map(
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USER_SIGNAL_TO_GLOBAL_BUFFER => clk_out_i,
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GLOBAL_BUFFER_OUTPUT => clk_out
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);
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SB_GB2_inst : component SB_GB
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port map(
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USER_SIGNAL_TO_GLOBAL_BUFFER => clk_in,
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GLOBAL_BUFFER_OUTPUT => clk_out_phy
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);
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assert F_IN = 50000000 report "clk_in: PLL expects clock different from specified." severity failure;
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assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure;
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assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure;
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end Structure;
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