PCB, FPGA, and SW design to implement a tiny Ethernet-connected SoC based on SERV + Trashernet

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Markus Koch 876693ca5f fpga: uart_wb: Latch received byte to allow late retrieval of data Else, the CPU would get the part old / half current byte. This enables boot loader baud rates in excess of 19200 baud.		2024-08-09 11:29:33 +02:00
fpga	fpga: uart_wb: Latch received byte to allow late retrieval of data	2024-08-09 11:29:33 +02:00
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.gitmodules	fpga: Implement basic SERV SoC	2024-06-22 11:28:15 +02:00
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README.MD	fpga: Implement basic SERV SoC	2024-06-22 11:28:15 +02:00

README.MD

Trashernet SoC

PCB, FPGA, and SW design to implement a tiny Ethernet-connected SoC based on SERV + Trashernet.

License

Hardware

The PCB design in /kicad is released under a Creative Commons Attribution-ShareAlike 4.0 International license.

You can find a copy of the full license in LICENSE-CC-BY-SA-4.0.TXT.

FPGA

The FPGA Source Code Form in /fpga is subject to the terms of the Mozilla Public License, v. 2.0.

You can find a copy of the full license in LICENSE-MPL-2.0.txt.

Note that this design incorporates code from third-party projects, which may come with further restrictions. For details, refer to the individual projects's licensing terms:

SERV: ISC License
Trashernet: Mozilla Public License, v. 2.0.

SW

TBD.