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trashernet-soc/fpga
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Markus Koch 8cf103a18d fpga: neorv32: Disable reset of regfile
2024-09-27 16:35:18 +02:00
..
.settings
fpga: Add Sigasi / Code project
2024-09-27 14:47:45 +02:00
hdl
fpga: neorv32: Disable reset of regfile
2024-09-27 16:35:18 +02:00
.gitignore
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
.library_mapping.xml
fpga: Add Sigasi / Code project
2024-09-27 14:47:45 +02:00
.project
fpga: Add Sigasi / Code project
2024-09-27 14:47:45 +02:00
constraints.pcf
fpga: Clean up clocking code
2024-08-09 14:01:16 +02:00
Makefile
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
run_physical.py
fpga: Add NEORV32 as alternative CPU core
2024-09-27 14:44:28 +02:00
run.py
fpga: Add NEORV32 as alternative CPU core
2024-09-27 14:44:28 +02:00
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