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8cf103a18d
trashernet-soc
/
fpga
/
hdl
History
Markus Koch
8cf103a18d
fpga: neorv32: Disable reset of regfile
2024-09-27 16:35:18 +02:00
..
bench
fpga: bench: Add self-checking test bench for bootrom
2024-09-27 14:45:07 +02:00
design
fpga: neorv32: Disable reset of regfile
2024-09-27 16:35:18 +02:00
device_models
fpga: aps6404l device model: Remove unnecessary newlines
2024-08-01 21:11:47 +02:00
generics
fpga: Clean up clocking code
2024-08-09 14:01:16 +02:00
neorv32
@
fd79163eb2
fpga: Add NEORV32 as alternative CPU core
2024-09-27 14:44:28 +02:00
serv
@
086090046c
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00
trashernet
@
206332f3d1
fpga: Implement functional Ethernet controller
2024-07-23 19:13:42 +02:00
header.sh
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00