trashernet-soc/fpga/hdl/design/pll0.vhd

26 lines
787 B
VHDL

-- -------------------------------------------------------------------------- --
-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
-- -------------------------------------------------------------------------- --
-- TODO
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library IEEE;
use IEEE.std_logic_1164.all;
entity pll0 is
port(
CLKI : in std_logic;
CLKOP : out std_logic;
LOCK : out std_logic);
end pll0;
architecture Structure of pll0 is
begin
CLKOP <= CLKI;
LOCK <= '1';
end Structure;