Markus Koch 9487f5c2ef fpga: top: Refactor indentation		2024-11-08 15:52:46 +01:00
..
aps6404l_controller.vhd	fpga: aps6404l_controller: Add generic to select wrap mode	2024-08-01 21:03:12 +02:00
aps6404l_wb.vhd	fpga: aps6404l_wb: Fix memory arbitration bug	2024-08-14 19:15:57 +02:00
neorv32_top.vhd	fpga: neorv32: Disable reset of regfile	2024-09-27 16:35:18 +02:00
pll0.vhd	fpga: Clean up clocking code	2024-08-09 14:01:16 +02:00
ram_vhdl.vhd	fpga: ram: Use Verilog model for synthesis and VHDL for simulation	2024-09-27 16:34:55 +02:00
serv_top_vhdl.vhd	fpga: Implement basic SERV SoC	2024-06-22 11:28:15 +02:00
servant_gpio_vhdl.vhd	fpga: Implement basic SERV SoC	2024-06-22 11:28:15 +02:00
servant_ram.vhd	fpga: ram: Use Verilog model for synthesis and VHDL for simulation	2024-09-27 16:34:55 +02:00
servant_timer_vhdl.vhd	fpga: Implement basic SERV SoC	2024-06-22 11:28:15 +02:00
top.vhd	fpga: top: Refactor indentation	2024-11-08 15:52:46 +01:00
trashernet_phy_wb.vhd	fpga: trashernet_phy_wb: Ensure LEDs blink even with constant traffic	2024-08-01 21:10:53 +02:00
uart_wb.vhd	fpga: uart_wb: Latch received byte to allow late retrieval of data	2024-08-09 11:29:33 +02:00