trashernet-soc/fpga/hdl
2024-09-27 14:42:38 +02:00
..
bench fpga: bench: Fix top level clock pin name 2024-09-27 14:42:15 +02:00
design fpga: servant_ram: Rewrite in VHDL 2024-09-27 14:42:38 +02:00
device_models fpga: aps6404l device model: Remove unnecessary newlines 2024-08-01 21:11:47 +02:00
generics fpga: Clean up clocking code 2024-08-09 14:01:16 +02:00
serv@086090046c fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00
trashernet@206332f3d1 fpga: Implement functional Ethernet controller 2024-07-23 19:13:42 +02:00
header.sh fpga: Implement basic SERV SoC 2024-06-22 11:28:15 +02:00