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bb7b2a7a10
trashernet-soc
/
fpga
/
hdl
/
bench
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Markus Koch
0545769bcd
fpga: bench: Fix top level clock pin name
2024-09-27 14:42:15 +02:00
..
bench_aps6404l_controller.vhd
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00
bench_aps6404l_wb.vhd
fpga: Implement single-instruction prefetching from external RAM
2024-08-01 21:06:14 +02:00
bench_fifo_block.vhd
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00
bench_top_manual.vhd
fpga: bench: Fix top level clock pin name
2024-09-27 14:42:15 +02:00