electronics/ttl-fpga
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2 Commits
dc5b791b6d ... 9f96e5cf82

Author SHA1 Message Date
Markus Koch
9f96e5cf82 Editiorial 2019-06-13 19:19:26 +02:00
Markus Koch
01043be425 Remove incorrect junction 
Fixes #7.
 2019-06-13 19:18:58 +02:00
2 changed files with 10 additions and 13 deletions
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7
kicad_clean/logic_block.sch
View File

@ -2447,10 +2447,6 @@ Text Label 13000 7750 1 50 Italic 0
fabric_b0
Text Label 14650 6050 0 50 Italic 0
fabric_r0
Wire Wire Line
14350 6050 14350 5600
Wire Wire Line
14350 7400 14350 6050
Wire Wire Line
14650 6500 13450 6500
Wire Wire Line
@ -2461,7 +2457,6 @@ Text Label 14650 6950 0 50 Italic 0
fabric_r2
Text Label 14650 7400 0 50 Italic 0
fabric_r3
Connection ~ 14350 6050
Wire Wire Line
14350 6050 14650 6050
$Sheet
@ -2527,4 +2522,6 @@ Wire Bus Line
7750 1800 7750 4350
Wire Bus Line
5900 1800 5900 4350
Wire Wire Line
14350 5600 14350 7400
$EndSCHEMATC

16
kicad_clean/ttl-fpga.sch
View File

@ -581,14 +581,6 @@ F 3 "" H 3550 5400 50 0001 C CNN
1 3550 5400
1 0 0 -1
$EndComp
Wire Bus Line
6150 2600 6900 2600
Wire Bus Line
6150 5050 6900 5050
Wire Bus Line
3900 4250 3900 4550
Wire Bus Line
7450 4250 7450 4550
Wire Wire Line
4150 5350 4150 5400
$Comp
@ -602,4 +594,12 @@ F 3 "" H 4150 5400 50 0001 C CNN
1 4150 5400
1 0 0 -1
$EndComp
Wire Bus Line
7450 4250 7450 4550
Wire Bus Line
3900 4250 3900 4550
Wire Bus Line
6150 2600 6900 2600
Wire Bus Line
6150 5050 6900 5050
$EndSCHEMATC